Merge tag 'drm-intel-fixes-2020-01-09-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- Fix GitLab issue #446 causing GPU hangs: Do not restore invalid RS state
- Fix GitLab issue #846: Restore coarse power gating that was disabled
by initial RC66 context corruption security fixes.
- Revert f6ec948309 ("drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms")
to avoid screen flicker
- Fix to fill in unitialized uabi_instance in virtual engine uAPI
- Add two missing W/As for ICL and EHL
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200109133458.GA15558@jlahtine-desk.ger.corp.intel.com
This commit is contained in:
Dave Airlie
Коммит
023b3b0e13
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@ -856,7 +856,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
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}
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/* Force CDCLK to 2*BCLK as long as we need audio powered. */
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, true);
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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@ -875,7 +875,7 @@ static void i915_audio_component_put_power(struct device *kdev,
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/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
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if (--dev_priv->audio_power_refcount == 0)
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if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
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if (IS_GEMINILAKE(dev_priv))
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glk_force_audio_cdclk(dev_priv, false);
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intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
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@ -4515,8 +4515,6 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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i915_reg_t reg;
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u32 trans_ddi_func_ctl2_val;
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if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
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return;
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@ -4524,10 +4522,7 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_
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DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
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transcoder_name(old_crtc_state->cpu_transcoder));
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reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder);
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trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE |
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PORT_SYNC_MODE_MASTER_SELECT_MASK);
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I915_WRITE(reg, trans_ddi_func_ctl2_val);
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I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0);
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}
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static void intel_fdi_normal_train(struct intel_crtc *crtc)
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@ -4416,9 +4416,11 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx,
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ve->base.gt = siblings[0]->gt;
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ve->base.uncore = siblings[0]->uncore;
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ve->base.id = -1;
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ve->base.class = OTHER_CLASS;
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ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
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ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
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ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
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/*
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* The decision on whether to submit a request using semaphores
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@ -1413,14 +1413,6 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
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int len;
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u32 *cs;
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flags |= MI_MM_SPACE_GTT;
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if (IS_HASWELL(i915))
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/* These flags are for resource streamer on HSW+ */
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flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
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else
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/* We need to save the extended state for powersaving modes */
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flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
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len = 4;
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if (IS_GEN(i915, 7))
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len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
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@ -1589,22 +1581,21 @@ static int switch_context(struct i915_request *rq)
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}
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if (ce->state) {
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u32 hw_flags;
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u32 flags;
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GEM_BUG_ON(rq->engine->id != RCS0);
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/*
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* The kernel context(s) is treated as pure scratch and is not
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* expected to retain any state (as we sacrifice it during
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* suspend and on resume it may be corrupted). This is ok,
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* as nothing actually executes using the kernel context; it
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* is purely used for flushing user contexts.
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*/
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hw_flags = 0;
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if (i915_gem_context_is_kernel(rq->gem_context))
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hw_flags = MI_RESTORE_INHIBIT;
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/* For resource streamer on HSW+ and power context elsewhere */
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BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);
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BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);
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ret = mi_set_context(rq, hw_flags);
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flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;
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if (!i915_gem_context_is_kernel(rq->gem_context))
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flags |= MI_RESTORE_EXT_STATE_EN;
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else
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flags |= MI_RESTORE_INHIBIT;
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ret = mi_set_context(rq, flags);
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if (ret)
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return ret;
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}
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@ -1660,8 +1660,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
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/* WaRsDisableCoarsePowerGating:skl,cnl */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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(IS_CANNONLAKE(dev_priv) || \
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IS_SKL_GT3(dev_priv) || \
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IS_SKL_GT4(dev_priv))
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#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
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#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
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@ -4177,7 +4177,13 @@ enum {
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#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
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#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
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#define VFUNIT_CLKGATE_DIS (1 << 20)
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#define VFUNIT_CLKGATE_DIS REG_BIT(20)
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#define HSUNIT_CLKGATE_DIS REG_BIT(8)
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#define VSUNIT_CLKGATE_DIS REG_BIT(3)
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#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
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#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
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#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
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#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
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#define CGPSF_CLKGATE_DIS (1 << 3)
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@ -6565,6 +6565,17 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
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/* WaEnable32PlaneMode:icl */
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I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
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_MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
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/*
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* Wa_1408615072:icl,ehl (vsunit)
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* Wa_1407596294:icl,ehl (hsunit)
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*/
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE,
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0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
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/* Wa_1407352427:icl,ehl */
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intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
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0, PSDUNIT_CLKGATE_DIS);
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}
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static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
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