ARM: S5PC100: Add SPI clkdev support
Registered the SPI bus clocks with clkdev using generic connection id. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Padmavathi Venna
Kukjin Kim
Родитель
ba47917c68
Коммит
02717bb9aa
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@ -654,24 +654,6 @@ static struct clk init_clocks_off[] = {
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.parent = &clk_div_pclkd1.clk,
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.enable = s5pc100_d1_5_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.1",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.2",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 9),
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}, {
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.name = "mmc_48m",
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.devname = "s3c-sdhci.0",
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@ -717,6 +699,30 @@ static struct clk clk_hsmmc0 = {
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.ctrlbit = (1 << 5),
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};
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static struct clk clk_48m_spi0 = {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.0",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 7),
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};
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static struct clk clk_48m_spi1 = {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.1",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 8),
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};
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static struct clk clk_48m_spi2 = {
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.name = "spi_48m",
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.devname = "s3c64xx-spi.2",
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.parent = &clk_mout_48m.clk,
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.enable = s5pc100_sclk0_ctrl,
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.ctrlbit = (1 << 9),
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};
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static struct clk clk_vclk54m = {
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.name = "vclk_54m",
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.rate = 54000000,
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@ -934,39 +940,6 @@ static struct clksrc_clk clk_sclk_spdif = {
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 4),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 5),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.2",
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.ctrlbit = (1 << 6),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mixer",
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.ctrlbit = (1 << 6),
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@ -1108,6 +1081,42 @@ static struct clksrc_clk clk_sclk_mmc2 = {
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi0 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.0",
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.ctrlbit = (1 << 4),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi1 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.1",
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.ctrlbit = (1 << 5),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_sclk_spi2 = {
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.clk = {
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.name = "sclk_spi",
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.devname = "s3c64xx-spi.2",
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.ctrlbit = (1 << 6),
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.enable = s5pc100_sclk0_ctrl,
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},
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.sources = &clk_src_group1,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
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};
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/* Clock initialisation code */
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static struct clksrc_clk *sysclks[] = {
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&clk_mout_apll,
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@ -1141,6 +1150,9 @@ static struct clk *clk_cdev[] = {
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&clk_hsmmc0,
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&clk_hsmmc1,
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&clk_hsmmc2,
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&clk_48m_spi0,
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&clk_48m_spi1,
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&clk_48m_spi2,
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};
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static struct clksrc_clk *clksrc_cdev[] = {
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@ -1148,6 +1160,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
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&clk_sclk_mmc0,
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&clk_sclk_mmc1,
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&clk_sclk_mmc2,
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&clk_sclk_spi0,
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&clk_sclk_spi1,
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&clk_sclk_spi2,
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};
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void __init_or_cpufreq s5pc100_setup_clocks(void)
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@ -1298,6 +1313,13 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
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CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
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CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
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CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
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CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
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CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
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CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
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};
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void __init s5pc100_register_clocks(void)
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