spi: pic32: switch to use modern name
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230818093154.1183529-5-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Родитель
cc64ab491b
Коммит
0273727c3b
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@ -100,7 +100,7 @@ struct pic32_spi {
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int tx_irq;
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u32 fifo_n_byte; /* FIFO depth in bytes */
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struct clk *clk;
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struct spi_master *master;
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struct spi_controller *host;
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/* Current controller setting */
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u32 speed_hz; /* spi-clk rate */
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u32 mode;
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@ -224,9 +224,9 @@ static void pic32_err_stop(struct pic32_spi *pic32s, const char *msg)
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disable_irq_nosync(pic32s->tx_irq);
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/* Show err message and abort xfer with err */
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dev_err(&pic32s->master->dev, "%s\n", msg);
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if (pic32s->master->cur_msg)
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pic32s->master->cur_msg->status = -EIO;
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dev_err(&pic32s->host->dev, "%s\n", msg);
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if (pic32s->host->cur_msg)
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pic32s->host->cur_msg->status = -EIO;
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complete(&pic32s->xfer_done);
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}
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@ -250,7 +250,7 @@ static irqreturn_t pic32_spi_fault_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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if (!pic32s->master->cur_msg) {
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if (!pic32s->host->cur_msg) {
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pic32_err_stop(pic32s, "err_irq: no mesg");
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return IRQ_NONE;
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}
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@ -300,16 +300,16 @@ static void pic32_spi_dma_rx_notify(void *data)
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static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
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struct spi_transfer *xfer)
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{
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struct spi_master *master = pic32s->master;
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struct spi_controller *host = pic32s->host;
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struct dma_async_tx_descriptor *desc_rx;
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struct dma_async_tx_descriptor *desc_tx;
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dma_cookie_t cookie;
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int ret;
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if (!master->dma_rx || !master->dma_tx)
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if (!host->dma_rx || !host->dma_tx)
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return -ENODEV;
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desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
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desc_rx = dmaengine_prep_slave_sg(host->dma_rx,
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xfer->rx_sg.sgl,
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xfer->rx_sg.nents,
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DMA_DEV_TO_MEM,
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@ -319,7 +319,7 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
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goto err_dma;
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}
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desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
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desc_tx = dmaengine_prep_slave_sg(host->dma_tx,
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xfer->tx_sg.sgl,
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xfer->tx_sg.nents,
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DMA_MEM_TO_DEV,
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@ -343,13 +343,13 @@ static int pic32_spi_dma_transfer(struct pic32_spi *pic32s,
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if (ret)
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goto err_dma_tx;
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dma_async_issue_pending(master->dma_rx);
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dma_async_issue_pending(master->dma_tx);
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dma_async_issue_pending(host->dma_rx);
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dma_async_issue_pending(host->dma_tx);
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return 0;
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err_dma_tx:
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dmaengine_terminate_all(master->dma_rx);
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dmaengine_terminate_all(host->dma_rx);
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err_dma:
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return ret;
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}
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@ -357,7 +357,7 @@ err_dma:
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static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
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{
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int buf_offset = offsetof(struct pic32_spi_regs, buf);
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struct spi_master *master = pic32s->master;
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struct spi_controller *host = pic32s->host;
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struct dma_slave_config cfg;
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int ret;
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@ -371,16 +371,16 @@ static int pic32_spi_dma_config(struct pic32_spi *pic32s, u32 dma_width)
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cfg.dst_addr_width = dma_width;
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/* tx channel */
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cfg.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(master->dma_tx, &cfg);
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ret = dmaengine_slave_config(host->dma_tx, &cfg);
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if (ret) {
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dev_err(&master->dev, "tx channel setup failed\n");
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dev_err(&host->dev, "tx channel setup failed\n");
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return ret;
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}
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/* rx channel */
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cfg.direction = DMA_DEV_TO_MEM;
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ret = dmaengine_slave_config(master->dma_rx, &cfg);
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ret = dmaengine_slave_config(host->dma_rx, &cfg);
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if (ret)
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dev_err(&master->dev, "rx channel setup failed\n");
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dev_err(&host->dev, "rx channel setup failed\n");
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return ret;
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}
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@ -430,19 +430,19 @@ static int pic32_spi_set_word_size(struct pic32_spi *pic32s, u8 bits_per_word)
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return 0;
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}
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static int pic32_spi_prepare_hardware(struct spi_master *master)
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static int pic32_spi_prepare_hardware(struct spi_controller *host)
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{
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struct pic32_spi *pic32s = spi_master_get_devdata(master);
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struct pic32_spi *pic32s = spi_controller_get_devdata(host);
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pic32_spi_enable(pic32s);
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return 0;
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}
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static int pic32_spi_prepare_message(struct spi_master *master,
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static int pic32_spi_prepare_message(struct spi_controller *host,
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struct spi_message *msg)
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{
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struct pic32_spi *pic32s = spi_master_get_devdata(master);
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struct pic32_spi *pic32s = spi_controller_get_devdata(host);
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struct spi_device *spi = msg->spi;
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u32 val;
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@ -481,18 +481,18 @@ static int pic32_spi_prepare_message(struct spi_master *master,
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return 0;
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}
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static bool pic32_spi_can_dma(struct spi_master *master,
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static bool pic32_spi_can_dma(struct spi_controller *host,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct pic32_spi *pic32s = spi_master_get_devdata(master);
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struct pic32_spi *pic32s = spi_controller_get_devdata(host);
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/* skip using DMA on small size transfer to avoid overhead.*/
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return (xfer->len >= PIC32_DMA_LEN_MIN) &&
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test_bit(PIC32F_DMA_PREP, &pic32s->flags);
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}
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static int pic32_spi_one_transfer(struct spi_master *master,
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static int pic32_spi_one_transfer(struct spi_controller *host,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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@ -501,7 +501,7 @@ static int pic32_spi_one_transfer(struct spi_master *master,
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unsigned long timeout;
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int ret;
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pic32s = spi_master_get_devdata(master);
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pic32s = spi_controller_get_devdata(host);
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/* handle transfer specific word size change */
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if (transfer->bits_per_word &&
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@ -549,8 +549,8 @@ static int pic32_spi_one_transfer(struct spi_master *master,
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if (timeout == 0) {
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dev_err(&spi->dev, "wait error/timedout\n");
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if (dma_issued) {
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dmaengine_terminate_all(master->dma_rx);
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dmaengine_terminate_all(master->dma_tx);
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dmaengine_terminate_all(host->dma_rx);
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dmaengine_terminate_all(host->dma_tx);
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}
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ret = -ETIMEDOUT;
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} else {
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@ -560,16 +560,16 @@ static int pic32_spi_one_transfer(struct spi_master *master,
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return ret;
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}
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static int pic32_spi_unprepare_message(struct spi_master *master,
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static int pic32_spi_unprepare_message(struct spi_controller *host,
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struct spi_message *msg)
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{
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/* nothing to do */
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return 0;
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}
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static int pic32_spi_unprepare_hardware(struct spi_master *master)
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static int pic32_spi_unprepare_hardware(struct spi_controller *host)
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{
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struct pic32_spi *pic32s = spi_master_get_devdata(master);
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struct pic32_spi *pic32s = spi_controller_get_devdata(host);
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pic32_spi_disable(pic32s);
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@ -605,28 +605,28 @@ static void pic32_spi_cleanup(struct spi_device *spi)
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static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
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{
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struct spi_master *master = pic32s->master;
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struct spi_controller *host = pic32s->host;
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int ret = 0;
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master->dma_rx = dma_request_chan(dev, "spi-rx");
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if (IS_ERR(master->dma_rx)) {
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if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER)
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host->dma_rx = dma_request_chan(dev, "spi-rx");
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if (IS_ERR(host->dma_rx)) {
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if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER)
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ret = -EPROBE_DEFER;
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else
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dev_warn(dev, "RX channel not found.\n");
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master->dma_rx = NULL;
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host->dma_rx = NULL;
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goto out_err;
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}
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master->dma_tx = dma_request_chan(dev, "spi-tx");
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if (IS_ERR(master->dma_tx)) {
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if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER)
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host->dma_tx = dma_request_chan(dev, "spi-tx");
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if (IS_ERR(host->dma_tx)) {
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if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER)
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ret = -EPROBE_DEFER;
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else
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dev_warn(dev, "TX channel not found.\n");
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master->dma_tx = NULL;
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host->dma_tx = NULL;
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goto out_err;
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}
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@ -639,14 +639,14 @@ static int pic32_spi_dma_prep(struct pic32_spi *pic32s, struct device *dev)
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return 0;
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out_err:
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if (master->dma_rx) {
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dma_release_channel(master->dma_rx);
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master->dma_rx = NULL;
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if (host->dma_rx) {
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dma_release_channel(host->dma_rx);
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host->dma_rx = NULL;
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}
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if (master->dma_tx) {
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dma_release_channel(master->dma_tx);
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master->dma_tx = NULL;
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if (host->dma_tx) {
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dma_release_channel(host->dma_tx);
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host->dma_tx = NULL;
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}
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return ret;
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@ -658,11 +658,11 @@ static void pic32_spi_dma_unprep(struct pic32_spi *pic32s)
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return;
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clear_bit(PIC32F_DMA_PREP, &pic32s->flags);
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if (pic32s->master->dma_rx)
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dma_release_channel(pic32s->master->dma_rx);
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if (pic32s->host->dma_rx)
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dma_release_channel(pic32s->host->dma_rx);
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if (pic32s->master->dma_tx)
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dma_release_channel(pic32s->master->dma_tx);
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if (pic32s->host->dma_tx)
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dma_release_channel(pic32s->host->dma_tx);
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}
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static void pic32_spi_hw_init(struct pic32_spi *pic32s)
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@ -680,7 +680,7 @@ static void pic32_spi_hw_init(struct pic32_spi *pic32s)
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/* disable framing mode */
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ctrl &= ~CTRL_FRMEN;
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/* enable master mode while disabled */
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/* enable host mode while disabled */
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ctrl |= CTRL_MSTEN;
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/* set tx fifo threshold interrupt */
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@ -752,36 +752,36 @@ err_unmap_mem:
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static int pic32_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct spi_controller *host;
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struct pic32_spi *pic32s;
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int ret;
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master = spi_alloc_master(&pdev->dev, sizeof(*pic32s));
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if (!master)
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host = spi_alloc_host(&pdev->dev, sizeof(*pic32s));
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if (!host)
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return -ENOMEM;
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pic32s = spi_master_get_devdata(master);
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pic32s->master = master;
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pic32s = spi_controller_get_devdata(host);
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pic32s->host = host;
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ret = pic32_spi_hw_probe(pdev, pic32s);
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if (ret)
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goto err_master;
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goto err_host;
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master->dev.of_node = pdev->dev.of_node;
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master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
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master->num_chipselect = 1; /* single chip-select */
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master->max_speed_hz = clk_get_rate(pic32s->clk);
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master->setup = pic32_spi_setup;
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master->cleanup = pic32_spi_cleanup;
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master->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
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host->dev.of_node = pdev->dev.of_node;
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host->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH;
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host->num_chipselect = 1; /* single chip-select */
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host->max_speed_hz = clk_get_rate(pic32s->clk);
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host->setup = pic32_spi_setup;
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host->cleanup = pic32_spi_cleanup;
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host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_MUST_RX;
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host->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
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SPI_BPW_MASK(32);
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master->transfer_one = pic32_spi_one_transfer;
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master->prepare_message = pic32_spi_prepare_message;
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master->unprepare_message = pic32_spi_unprepare_message;
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master->prepare_transfer_hardware = pic32_spi_prepare_hardware;
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master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
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master->use_gpio_descriptors = true;
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host->transfer_one = pic32_spi_one_transfer;
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host->prepare_message = pic32_spi_prepare_message;
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host->unprepare_message = pic32_spi_unprepare_message;
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host->prepare_transfer_hardware = pic32_spi_prepare_hardware;
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host->unprepare_transfer_hardware = pic32_spi_unprepare_hardware;
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host->use_gpio_descriptors = true;
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/* optional DMA support */
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ret = pic32_spi_dma_prep(pic32s, &pdev->dev);
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@ -789,7 +789,7 @@ static int pic32_spi_probe(struct platform_device *pdev)
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goto err_bailout;
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if (test_bit(PIC32F_DMA_PREP, &pic32s->flags))
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master->can_dma = pic32_spi_can_dma;
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host->can_dma = pic32_spi_can_dma;
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init_completion(&pic32s->xfer_done);
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pic32s->mode = -1;
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@ -824,10 +824,10 @@ static int pic32_spi_probe(struct platform_device *pdev)
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goto err_bailout;
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}
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/* register master */
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ret = devm_spi_register_master(&pdev->dev, master);
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/* register host */
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ret = devm_spi_register_controller(&pdev->dev, host);
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if (ret) {
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dev_err(&master->dev, "failed registering spi master\n");
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dev_err(&host->dev, "failed registering spi host\n");
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goto err_bailout;
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}
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@ -838,8 +838,8 @@ static int pic32_spi_probe(struct platform_device *pdev)
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err_bailout:
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pic32_spi_dma_unprep(pic32s);
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clk_disable_unprepare(pic32s->clk);
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err_master:
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spi_master_put(master);
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err_host:
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spi_controller_put(host);
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return ret;
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}
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