avr32: Power Management support ("standby" and "mem" modes)
Implement Standby support. In this mode, we'll suspend all drivers,
put the SDRAM in self-refresh mode and switch off the HSB bus
("frozen" mode.)
Implement Suspend-to-mem support. In this mode, we suspend all
drivers, put the SDRAM into self-refresh mode and switch off all
internal clocks except the 32 kHz oscillator ("stop" mode.)
The lowest-level suspend code runs from a small portion of SRAM
allocated at startup time. This gets rid of a small potential race
with the SDRAM where we might try to enter self-refresh mode in the
middle of an icache burst. We also relocate all interrupt and
exception handlers to SRAM during the small window when we enter and
exit the low-power modes.
We don't need to do any special tricks to start and stop the PLL. The
main clock is automatically gated by hardware until the PLL is stable.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
Haavard Skinnemoen
Родитель
aa8e87ca61
Коммит
02a00cf672
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@ -205,6 +205,11 @@ endmenu
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menu "Power management options"
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source "kernel/power/Kconfig"
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config ARCH_SUSPEND_POSSIBLE
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def_bool y
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menu "CPU Frequency scaling"
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source "drivers/cpufreq/Kconfig"
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|
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@ -1,3 +1,8 @@
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obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
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obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
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obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
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obj-$(CONFIG_PM) += pm.o
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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endif
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|
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@ -22,6 +22,10 @@ struct intc {
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void __iomem *regs;
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struct irq_chip chip;
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struct sys_device sysdev;
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#ifdef CONFIG_PM
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unsigned long suspend_ipr;
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unsigned long saved_ipr[64];
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#endif
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};
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extern struct platform_device at32_intc0_device;
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@ -138,8 +142,56 @@ fail:
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panic("Interrupt controller initialization failed!\n");
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}
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#ifdef CONFIG_PM
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void intc_set_suspend_handler(unsigned long offset)
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{
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intc0.suspend_ipr = offset;
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}
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static int intc_suspend(struct sys_device *sdev, pm_message_t state)
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{
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struct intc *intc = container_of(sdev, struct intc, sysdev);
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int i;
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if (unlikely(!irqs_disabled())) {
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pr_err("intc_suspend: called with interrupts enabled\n");
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return -EINVAL;
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}
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if (unlikely(!intc->suspend_ipr)) {
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pr_err("intc_suspend: suspend_ipr not initialized\n");
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return -EINVAL;
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}
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for (i = 0; i < 64; i++) {
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intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
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intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
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}
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return 0;
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}
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static int intc_resume(struct sys_device *sdev)
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{
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struct intc *intc = container_of(sdev, struct intc, sysdev);
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int i;
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WARN_ON(!irqs_disabled());
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for (i = 0; i < 64; i++)
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intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
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return 0;
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}
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#else
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#define intc_suspend NULL
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#define intc_resume NULL
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#endif
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static struct sysdev_class intc_class = {
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.name = "intc",
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.name = "intc",
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.suspend = intc_suspend,
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.resume = intc_resume,
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};
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static int __init intc_init_sysdev(void)
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@ -12,6 +12,12 @@
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#include <asm/thread_info.h>
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#include <asm/arch/pm.h>
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#include "pm.h"
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#include "sdramc.h"
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/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
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#define PM_BASE -0x100000
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.section .bss, "wa", @nobits
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.global disable_idle_sleep
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.type disable_idle_sleep, @object
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@ -64,3 +70,105 @@ cpu_idle_skip_sleep:
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unmask_interrupts
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retal r12
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.size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
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#ifdef CONFIG_PM
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.section .init.text, "ax", @progbits
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.global pm_exception
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.type pm_exception, @function
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pm_exception:
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/*
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* Exceptions are masked when we switch to this handler, so
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* we'll only get "unrecoverable" exceptions (offset 0.)
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*/
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sub r12, pc, . - .Lpanic_msg
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lddpc pc, .Lpanic_addr
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.align 2
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.Lpanic_addr:
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.long panic
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.Lpanic_msg:
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.asciz "Unrecoverable exception during suspend\n"
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.size pm_exception, . - pm_exception
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.global pm_irq0
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.type pm_irq0, @function
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pm_irq0:
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/* Disable interrupts and return after the sleep instruction */
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mfsr r9, SYSREG_RSR_INT0
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mtsr SYSREG_RAR_INT0, r8
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sbr r9, SYSREG_GM_OFFSET
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mtsr SYSREG_RSR_INT0, r9
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rete
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/*
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* void cpu_enter_standby(unsigned long sdramc_base)
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*
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* Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
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* are suspended and interrupts are disabled. Interrupts
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* marked as 'wakeup' event sources may still come along and
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* get us out of here.
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*
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* The SDRAM will be put into self-refresh mode (which does
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* not require a clock from the CPU), and the CPU will be put
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* into "frozen" mode (HSB bus stopped). The SDRAM controller
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* will automatically bring the SDRAM into normal mode on the
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* first access, and the power manager will automatically
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* start the HSB and CPU clocks upon a wakeup event.
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*
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* This code uses the same "skip sleep" technique as above.
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* It is very important that we jump directly to
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* cpu_after_sleep after the sleep instruction since that's
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* where we'll end up if the interrupt handler decides that we
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* need to skip the sleep instruction.
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*/
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.global pm_standby
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.type pm_standby, @function
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pm_standby:
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/*
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* interrupts are already masked at this point, and EVBA
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* points to pm_exception above.
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*/
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ld.w r10, r12[SDRAMC_LPR]
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sub r8, pc, . - 1f /* return address for irq handler */
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mov r11, SDRAMC_LPR_LPCB_SELF_RFR
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bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
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sync 0 /* flush write buffer */
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st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */
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ld.w r11, r12[SDRAMC_LPR]
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unmask_interrupts
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sleep CPU_SLEEP_FROZEN
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1: mask_interrupts
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retal r12
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.size pm_standby, . - pm_standby
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.global pm_suspend_to_ram
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.type pm_suspend_to_ram, @function
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pm_suspend_to_ram:
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/*
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* interrupts are already masked at this point, and EVBA
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* points to pm_exception above.
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*/
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mov r11, 0
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cache r11[2], 8 /* clean all dcache lines */
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sync 0 /* flush write buffer */
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ld.w r10, r12[SDRAMC_LPR]
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sub r8, pc, . - 1f /* return address for irq handler */
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mov r11, SDRAMC_LPR_LPCB_SELF_RFR
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bfins r10, r11, 0, 2 /* LPCB <- self refresh */
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st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
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ld.w r11, r12[SDRAMC_LPR]
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unmask_interrupts
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sleep CPU_SLEEP_STOP
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1: mask_interrupts
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retal r12
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.size pm_suspend_to_ram, . - pm_suspend_to_ram
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.global pm_sram_end
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.type pm_sram_end, @function
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pm_sram_end:
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.size pm_sram_end, 0
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#endif /* CONFIG_PM */
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@ -0,0 +1,245 @@
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/*
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* AVR32 AP Power Management
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/suspend.h>
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#include <linux/vmalloc.h>
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#include <asm/cacheflush.h>
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#include <asm/sysreg.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/sram.h>
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/* FIXME: This is only valid for AP7000 */
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#define SDRAMC_BASE 0xfff03800
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#include "sdramc.h"
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#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
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| SYSREG_BF(AP, 3) | SYSREG_BIT(G))
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static unsigned long pm_sram_start;
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static size_t pm_sram_size;
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static struct vm_struct *pm_sram_area;
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static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
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static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
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/*
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* Must be called with interrupts disabled. Exceptions will be masked
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* on return (i.e. all exceptions will be "unrecoverable".)
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*/
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static void *avr32_pm_map_sram(void)
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{
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unsigned long vaddr;
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unsigned long page_addr;
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u32 tlbehi;
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u32 mmucr;
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vaddr = (unsigned long)pm_sram_area->addr;
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page_addr = pm_sram_start & PAGE_MASK;
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/*
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* Mask exceptions and grab the first TLB entry. We won't be
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* needing it while sleeping.
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*/
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asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
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mmucr = sysreg_read(MMUCR);
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tlbehi = sysreg_read(TLBEHI);
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sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
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tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
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tlbehi |= vaddr & PAGE_MASK;
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tlbehi |= SYSREG_BIT(TLBEHI_V);
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sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
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sysreg_write(TLBEHI, tlbehi);
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__builtin_tlbw();
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return (void *)(vaddr + pm_sram_start - page_addr);
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}
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|
||||
/*
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* Must be called with interrupts disabled. Exceptions will be
|
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* unmasked on return.
|
||||
*/
|
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static void avr32_pm_unmap_sram(void)
|
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{
|
||||
u32 mmucr;
|
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u32 tlbehi;
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u32 tlbarlo;
|
||||
|
||||
/* Going to update TLB entry at index 0 */
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||||
mmucr = sysreg_read(MMUCR);
|
||||
tlbehi = sysreg_read(TLBEHI);
|
||||
sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
|
||||
|
||||
/* Clear the "valid" bit */
|
||||
tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
|
||||
sysreg_write(TLBEHI, tlbehi);
|
||||
|
||||
/* Mark it as "not accessed" */
|
||||
tlbarlo = sysreg_read(TLBARLO);
|
||||
sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
|
||||
|
||||
/* Update the TLB */
|
||||
__builtin_tlbw();
|
||||
|
||||
/* Unmask exceptions */
|
||||
asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
|
||||
}
|
||||
|
||||
static int avr32_pm_valid_state(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_ON:
|
||||
case PM_SUSPEND_STANDBY:
|
||||
case PM_SUSPEND_MEM:
|
||||
return 1;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int avr32_pm_enter(suspend_state_t state)
|
||||
{
|
||||
u32 lpr_saved;
|
||||
u32 evba_saved;
|
||||
void *sram;
|
||||
|
||||
switch (state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
sram = avr32_pm_map_sram();
|
||||
|
||||
/* Switch to in-sram exception handlers */
|
||||
evba_saved = sysreg_read(EVBA);
|
||||
sysreg_write(EVBA, (unsigned long)sram);
|
||||
|
||||
/*
|
||||
* Save the LPR register so that we can re-enable
|
||||
* SDRAM Low Power mode on resume.
|
||||
*/
|
||||
lpr_saved = sdramc_readl(LPR);
|
||||
pr_debug("%s: Entering standby...\n", __func__);
|
||||
avr32_pm_enter_standby(SDRAMC_BASE);
|
||||
sdramc_writel(LPR, lpr_saved);
|
||||
|
||||
/* Switch back to regular exception handlers */
|
||||
sysreg_write(EVBA, evba_saved);
|
||||
|
||||
avr32_pm_unmap_sram();
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_MEM:
|
||||
sram = avr32_pm_map_sram();
|
||||
|
||||
/* Switch to in-sram exception handlers */
|
||||
evba_saved = sysreg_read(EVBA);
|
||||
sysreg_write(EVBA, (unsigned long)sram);
|
||||
|
||||
/*
|
||||
* Save the LPR register so that we can re-enable
|
||||
* SDRAM Low Power mode on resume.
|
||||
*/
|
||||
lpr_saved = sdramc_readl(LPR);
|
||||
pr_debug("%s: Entering suspend-to-ram...\n", __func__);
|
||||
avr32_pm_enter_str(SDRAMC_BASE);
|
||||
sdramc_writel(LPR, lpr_saved);
|
||||
|
||||
/* Switch back to regular exception handlers */
|
||||
sysreg_write(EVBA, evba_saved);
|
||||
|
||||
avr32_pm_unmap_sram();
|
||||
break;
|
||||
|
||||
case PM_SUSPEND_ON:
|
||||
pr_debug("%s: Entering idle...\n", __func__);
|
||||
cpu_enter_idle();
|
||||
break;
|
||||
|
||||
default:
|
||||
pr_debug("%s: Invalid suspend state %d\n", __func__, state);
|
||||
goto out;
|
||||
}
|
||||
|
||||
pr_debug("%s: wakeup\n", __func__);
|
||||
|
||||
out:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_suspend_ops avr32_pm_ops = {
|
||||
.valid = avr32_pm_valid_state,
|
||||
.enter = avr32_pm_enter,
|
||||
};
|
||||
|
||||
static unsigned long avr32_pm_offset(void *symbol)
|
||||
{
|
||||
extern u8 pm_exception[];
|
||||
|
||||
return (unsigned long)symbol - (unsigned long)pm_exception;
|
||||
}
|
||||
|
||||
static int __init avr32_pm_init(void)
|
||||
{
|
||||
extern u8 pm_exception[];
|
||||
extern u8 pm_irq0[];
|
||||
extern u8 pm_standby[];
|
||||
extern u8 pm_suspend_to_ram[];
|
||||
extern u8 pm_sram_end[];
|
||||
void *dst;
|
||||
|
||||
/*
|
||||
* To keep things simple, we depend on not needing more than a
|
||||
* single page.
|
||||
*/
|
||||
pm_sram_size = avr32_pm_offset(pm_sram_end);
|
||||
if (pm_sram_size > PAGE_SIZE)
|
||||
goto err;
|
||||
|
||||
pm_sram_start = sram_alloc(pm_sram_size);
|
||||
if (!pm_sram_start)
|
||||
goto err_alloc_sram;
|
||||
|
||||
/* Grab a virtual area we can use later on. */
|
||||
pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
|
||||
if (!pm_sram_area)
|
||||
goto err_vm_area;
|
||||
pm_sram_area->phys_addr = pm_sram_start;
|
||||
|
||||
local_irq_disable();
|
||||
dst = avr32_pm_map_sram();
|
||||
memcpy(dst, pm_exception, pm_sram_size);
|
||||
flush_dcache_region(dst, pm_sram_size);
|
||||
invalidate_icache_region(dst, pm_sram_size);
|
||||
avr32_pm_unmap_sram();
|
||||
local_irq_enable();
|
||||
|
||||
avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
|
||||
avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
|
||||
intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
|
||||
|
||||
suspend_set_ops(&avr32_pm_ops);
|
||||
|
||||
printk("AVR32 AP Power Management enabled\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_vm_area:
|
||||
sram_free(pm_sram_start, pm_sram_size);
|
||||
err_alloc_sram:
|
||||
err:
|
||||
pr_err("AVR32 Power Management initialization failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
arch_initcall(avr32_pm_init);
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Register definitions for the AT32AP SDRAM Controller
|
||||
*
|
||||
* Copyright (C) 2008 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* Register offsets */
|
||||
#define SDRAMC_MR 0x0000
|
||||
#define SDRAMC_TR 0x0004
|
||||
#define SDRAMC_CR 0x0008
|
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#define SDRAMC_HSR 0x000c
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#define SDRAMC_LPR 0x0010
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||||
#define SDRAMC_IER 0x0014
|
||||
#define SDRAMC_IDR 0x0018
|
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#define SDRAMC_IMR 0x001c
|
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#define SDRAMC_ISR 0x0020
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#define SDRAMC_MDR 0x0024
|
||||
|
||||
/* MR - Mode Register */
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#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
|
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#define SDRAMC_MR_MODE_NOP ( 1 << 0)
|
||||
#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
|
||||
#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
|
||||
#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
|
||||
#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
|
||||
#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
|
||||
|
||||
/* CR - Configuration Register */
|
||||
#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
|
||||
#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
|
||||
#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
|
||||
#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
|
||||
#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
|
||||
#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
|
||||
#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
|
||||
#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
|
||||
#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
|
||||
#define SDRAMC_CR_CAS(x) ((x) << 5)
|
||||
#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
|
||||
#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
|
||||
#define SDRAMC_CR_TWR(x) ((x) << 8)
|
||||
#define SDRAMC_CR_TRC(x) ((x) << 12)
|
||||
#define SDRAMC_CR_TRP(x) ((x) << 16)
|
||||
#define SDRAMC_CR_TRCD(x) ((x) << 20)
|
||||
#define SDRAMC_CR_TRAS(x) ((x) << 24)
|
||||
#define SDRAMC_CR_TXSR(x) ((x) << 28)
|
||||
|
||||
/* HSR - High Speed Register */
|
||||
#define SDRAMC_HSR_DA ( 1 << 0)
|
||||
|
||||
/* LPR - Low Power Register */
|
||||
#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
|
||||
#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
|
||||
#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
|
||||
#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
|
||||
#define SDRAMC_LPR_PASR(x) ((x) << 4)
|
||||
#define SDRAMC_LPR_TCSR(x) ((x) << 8)
|
||||
#define SDRAMC_LPR_DS(x) ((x) << 10)
|
||||
#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
|
||||
|
||||
/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
|
||||
#define SDRAMC_ISR_RES ( 1 << 0)
|
||||
|
||||
/* MDR - Memory Device Register */
|
||||
#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
|
||||
#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
|
||||
|
||||
/* Register access macros */
|
||||
#define sdramc_readl(reg) \
|
||||
__raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
|
||||
#define sdramc_writel(reg, value) \
|
||||
__raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
|
||||
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void cpu_enter_idle(void);
|
||||
extern void cpu_enter_standby(unsigned long sdramc_base);
|
||||
|
||||
extern bool disable_idle_sleep;
|
||||
|
||||
|
|
@ -43,6 +44,8 @@ static inline void cpu_idle_sleep(void)
|
|||
else
|
||||
cpu_enter_idle();
|
||||
}
|
||||
|
||||
void intc_set_suspend_handler(unsigned long offset);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_AVR32_ARCH_PM_H */
|
||||
|
|
|
|||
|
|
@ -88,6 +88,7 @@ static inline struct thread_info *current_thread_info(void)
|
|||
#define TIF_MEMDIE 6
|
||||
#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
|
||||
#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
|
||||
#define TIF_FREEZE 29
|
||||
#define TIF_DEBUG 30 /* debugging enabled */
|
||||
#define TIF_USERSPACE 31 /* true if FS sets userspace */
|
||||
|
||||
|
|
|
|||
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