ARM: v7 setup function should invalidate L1 cache
All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
Родитель
6a53bc7500
Коммит
02b4e2756e
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@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
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ifeq ($(CONFIG_ARCH_BRCMSTB),y)
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CFLAGS_platsmp-brcmstb.o += -march=armv7-a
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obj-y += brcmstb.o
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obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
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obj-$(CONFIG_SMP) += platsmp-brcmstb.o
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endif
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@ -1,19 +0,0 @@
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/*
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __BRCMSTB_H__
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#define __BRCMSTB_H__
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void brcmstb_secondary_startup(void);
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#endif /* __BRCMSTB_H__ */
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@ -1,33 +0,0 @@
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/*
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* SMP boot code for secondary CPUs
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* Based on arch/arm/mach-tegra/headsmp.S
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*
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* Copyright (C) 2010 NVIDIA, Inc.
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* Copyright (C) 2013-2014 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/assembler.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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.section ".text.head", "ax"
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ENTRY(brcmstb_secondary_startup)
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/*
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* Ensure CPU is in a sane state by disabling all IRQs and switching
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* into SVC mode.
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*/
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(brcmstb_secondary_startup)
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@ -30,8 +30,6 @@
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#include <asm/mach-types.h>
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#include <asm/smp_plat.h>
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#include "brcmstb.h"
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enum {
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ZONE_MAN_CLKEN_MASK = BIT(0),
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ZONE_MAN_RESET_CNTL_MASK = BIT(1),
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@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
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* Set the reset vector to point to the secondary_startup
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* routine
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*/
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cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
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cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
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/* Unhalt the cpu */
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cpu_rst_cfg_set(cpu, 0);
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@ -12,12 +12,6 @@
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#include <linux/init.h>
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#include <asm/assembler.h>
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ENTRY(berlin_secondary_startup)
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ARM_BE8(setend be)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(berlin_secondary_startup)
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/*
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* If the following instruction is set in the reset exception vector, CPUs
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* will fetch the value of the software reset address vector when being
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@ -22,7 +22,6 @@
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#define RESET_VECT 0x00
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#define SW_RESET_ADDR 0x94
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extern void berlin_secondary_startup(void);
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extern u32 boot_inst;
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static void __iomem *cpu_ctrl;
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@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
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* Write the secondary startup address into the SW reset address
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* vector. This is used by boot_inst.
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*/
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writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR);
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writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
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iounmap(vectors_base);
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unmap_scu:
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@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
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obj-y += hisilicon.o
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obj-$(CONFIG_MCPM) += platmcpm.o
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obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o hotplug.o
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@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
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extern int hi3xxx_cpu_kill(unsigned int cpu);
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extern void hi3xxx_set_cpu(int cpu, bool enable);
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extern void hisi_secondary_startup(void);
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extern struct smp_operations hix5hd2_smp_ops;
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extern void hix5hd2_set_cpu(int cpu, bool enable);
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extern void hix5hd2_cpu_die(unsigned int cpu);
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@ -1,16 +0,0 @@
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/*
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* Copyright (c) 2014 Hisilicon Limited.
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* Copyright (c) 2014 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__CPUINIT
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ENTRY(hisi_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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phys_addr_t jumpaddr;
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jumpaddr = virt_to_phys(hisi_secondary_startup);
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jumpaddr = virt_to_phys(secondary_startup);
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hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
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hix5hd2_set_cpu(cpu, true);
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
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struct device_node *node;
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jumpaddr = virt_to_phys(hisi_secondary_startup);
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jumpaddr = virt_to_phys(secondary_startup);
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hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
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node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
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@ -25,7 +25,6 @@ diag_reg_offset:
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.endm
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ENTRY(v7_secondary_startup)
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bl v7_invalidate_l1
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set_diag_reg
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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@ -21,7 +21,6 @@
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ENTRY(mvebu_cortex_a9_secondary_startup)
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ARM_BE8(setend be)
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bl v7_invalidate_l1
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bl armada_38x_scu_power_up
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b secondary_startup
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ENDPROC(mvebu_cortex_a9_secondary_startup)
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@ -15,7 +15,6 @@
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* ready for them to initialise.
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*/
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ENTRY(sirfsoc_secondary_startup)
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bl v7_invalidate_l1
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
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extern char rockchip_secondary_trampoline_end;
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extern unsigned long rockchip_boot_fn;
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extern void rockchip_secondary_startup(void);
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@ -15,14 +15,6 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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ENTRY(rockchip_secondary_startup)
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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ldr r1, =0x00000c09 @ Cortex-A9 primary part number
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teq r0, r1
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beq v7_invalidate_l1
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b secondary_startup
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ENDPROC(rockchip_secondary_startup)
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ENTRY(rockchip_secondary_trampoline)
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ldr pc, 1f
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ENDPROC(rockchip_secondary_trampoline)
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@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
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* sram_base_addr + 8: start address for pc
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* */
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udelay(10);
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writel(virt_to_phys(rockchip_secondary_startup),
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sram_base_addr + 8);
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writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
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writel(0xDEADBEAF, sram_base_addr + 4);
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dsb_sev();
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}
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@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
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}
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/* set the boot function for the sram code */
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rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
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rockchip_boot_fn = virt_to_phys(secondary_startup);
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/* copy the trampoline to sram, that runs during startup of the core */
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memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
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@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
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extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
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unsigned long arg);
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extern int shmobile_smp_cpu_disable(unsigned int cpu);
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extern void shmobile_invalidate_start(void);
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extern void shmobile_boot_scu(void);
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extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
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extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
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@ -22,7 +22,7 @@
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* Boot code for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* shmobile_invalidate_start that invalidates the cache and hands over control
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* secondary_startup that invalidates the cache and hands over control
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* to the common ARM startup code.
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*/
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ENTRY(shmobile_boot_scu)
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@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
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bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
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str r2, [r0, #8] @ write back
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b shmobile_invalidate_start
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b secondary_startup
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ENDPROC(shmobile_boot_scu)
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.text
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@ -16,13 +16,6 @@
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#ifdef CONFIG_SMP
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ENTRY(shmobile_invalidate_start)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(shmobile_invalidate_start)
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#endif
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/*
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* Reset vector for secondary CPUs.
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* This will be mapped at address 0 by SBAR register.
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@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
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int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/* For this particular CPU register boot vector */
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shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
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shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
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return apmu_wrap(cpu, apmu_power_on);
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}
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@ -31,7 +31,6 @@
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#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
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extern void socfpga_secondary_startup(void);
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extern void __iomem *socfpga_scu_base_addr;
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extern void socfpga_init_clocks(void);
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@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
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1: .long .
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.long socfpga_cpu1start_addr
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ENTRY(secondary_trampoline_end)
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ENTRY(socfpga_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(socfpga_secondary_startup)
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@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
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writel(virt_to_phys(socfpga_secondary_startup),
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writel(virt_to_phys(secondary_startup),
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sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
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flush_cache_all();
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@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
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endif
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
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@ -1,12 +0,0 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include "sleep.h"
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.section ".text.head", "ax"
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ENTRY(tegra_secondary_startup)
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check_cpu_part_num 0xc09, r8, r9
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bleq v7_invalidate_l1
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
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__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
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*((u32 *)cpu_possible_mask);
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__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
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virt_to_phys((void *)tegra_secondary_startup);
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virt_to_phys((void *)secondary_startup);
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#endif
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#ifdef CONFIG_PM_SLEEP
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@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra_cpu_reset_handler_end(void);
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void tegra_secondary_startup(void);
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|
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask \
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|
|
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@ -17,8 +17,6 @@
|
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#ifndef __MACH_ZYNQ_COMMON_H__
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#define __MACH_ZYNQ_COMMON_H__
|
||||
|
||||
void zynq_secondary_startup(void);
|
||||
|
||||
extern int zynq_slcr_init(void);
|
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extern int zynq_early_slcr_init(void);
|
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extern void zynq_slcr_system_reset(void);
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||||
|
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|||
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@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
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.globl zynq_secondary_trampoline_end
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zynq_secondary_trampoline_end:
|
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ENDPROC(zynq_secondary_trampoline)
|
||||
|
||||
ENTRY(zynq_secondary_startup)
|
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bl v7_invalidate_l1
|
||||
b secondary_startup
|
||||
ENDPROC(zynq_secondary_startup)
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||||
|
|
|
|||
|
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@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
|
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}
|
||||
EXPORT_SYMBOL(zynq_cpun_start);
|
||||
|
||||
static int zynq_boot_secondary(unsigned int cpu,
|
||||
struct task_struct *idle)
|
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static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
{
|
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return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu);
|
||||
return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
|
||||
}
|
||||
|
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/*
|
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|
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@ -336,7 +336,7 @@ __v7_pj4b_setup:
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_louis
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bl v7_invalidate_l1
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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