powerpc/85xx: support for the TQM8548 module using the big Flash
Some TQM85xx boards could be equipped with up to 1 GiB (NOR) flash memory and therefore a modified memory map is required and setup by the board loader. This patch adds an appropriate DTS file. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Wolfgang Grandegger
Kumar Gala
Родитель
6dd1b64a26
Коммит
02b8a3d1eb
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/*
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* TQM8548 Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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* Copyright 2008 Wolfgang Grandegger <wg@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "tqc,tqm8548";
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compatible = "tqc,tqm8548";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8548@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000>; // Filled in by U-Boot
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};
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soc8548@a0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xa0000000 0x100000>;
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reg = <0xa0000000 0x1000>; // CCSRBAR
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,mpc8548-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8548-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy1: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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phy4: ethernet-phy@4 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <4>;
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device_type = "ethernet-phy";
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};
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phy5: ethernet-phy@5 {
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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reg = <5>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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enet2: ethernet@26000 {
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cell-index = <2>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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enet3: ethernet@27000 {
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cell-index = <3>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy4>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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current-speed = <115200>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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current-speed = <115200>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { // global utilities reg
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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localbus@a0005000 {
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compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
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"simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xa0005000 0x100>; // BRx, ORx, etc.
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ranges = <
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0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
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1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
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2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527)
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3 0x0 0xa3010000 0x00008000 // NAND FLASH
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>;
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flash@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <1 0x0 0x8000000>;
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bank-width = <4>;
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device-width = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00200000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x00300000>;
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};
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partition@500000 {
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label = "user";
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reg = <0x00500000 0x07a00000>;
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};
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partition@7f00000 {
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label = "env1";
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reg = <0x07f00000 0x00040000>;
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};
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partition@7f40000 {
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label = "env2";
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reg = <0x07f40000 0x00040000>;
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};
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partition@7f80000 {
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label = "u-boot";
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reg = <0x07f80000 0x00080000>;
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read-only;
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};
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};
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/* Note: CAN support needs be enabled in U-Boot */
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can0@2,0 {
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compatible = "intel,82527"; // Bosch CC770
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reg = <2 0x0 0x100>;
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interrupts = <4 0>;
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interrupt-parent = <&mpic>;
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};
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can1@2,100 {
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compatible = "intel,82527"; // Bosch CC770
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reg = <2 0x100 0x100>;
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interrupts = <4 0>;
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interrupt-parent = <&mpic>;
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};
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/* Note: NAND support needs to be enabled in U-Boot */
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upm@3,0 {
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#address-cells = <0>;
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#size-cells = <0>;
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compatible = "fsl,upm-nand";
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reg = <3 0x0 0x800>;
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fsl,upm-addr-offset = <0x10>;
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fsl,upm-cmd-offset = <0x08>;
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chip-delay = <25>; // in micro-seconds
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nand@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "fs";
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reg = <0x00000000 0x01000000>;
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};
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};
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};
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};
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pci0: pci@a0008000 {
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cell-index = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xa0008000 0x1000>;
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clock-frequency = <33333333>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 28 */
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0xe000 0 0 1 &mpic 2 1
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0xe000 0 0 2 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
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0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
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};
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pci1: pcie@a000a000 {
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cell-index = <2>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0 (PEX) */
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0x00000 0 0 1 &mpic 0 1
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0x00000 0 0 2 &mpic 1 1
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0x00000 0 0 3 &mpic 2 1
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0x00000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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bus-range = <0 0xff>;
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ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
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0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
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clock-frequency = <33333333>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xa000a000 0x1000>;
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compatible = "fsl,mpc8548-pcie";
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device_type = "pci";
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0 0xb0000000 0x02000000 0
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0xb0000000 0 0x10000000
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0x01000000 0 0x00000000 0x01000000 0
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0x00000000 0 0x08000000>;
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};
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};
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};
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