drm/radeon: rework UVD writeback & [rw]ptr handling
The hardware just doesn't support this correctly. Disable it before we accidentally write anywhere we shouldn't. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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76a0df859d
Коммит
02c9f7fa4e
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@ -7705,8 +7705,7 @@ static int cik_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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@ -5291,8 +5291,7 @@ static int evergreen_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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@ -2225,8 +2225,7 @@ static int cayman_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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@ -2623,31 +2623,38 @@ void r600_dma_fini(struct radeon_device *rdev)
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/*
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* UVD
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*/
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uint32_t r600_uvd_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return RREG32(UVD_RBC_RB_RPTR);
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}
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uint32_t r600_uvd_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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return RREG32(UVD_RBC_RB_WPTR);
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}
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void r600_uvd_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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WREG32(UVD_RBC_RB_WPTR, ring->wptr);
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}
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static int r600_uvd_rbc_start(struct radeon_device *rdev, bool ring_test)
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{
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struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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uint64_t rptr_addr;
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uint32_t rb_bufsz, tmp;
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int r;
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rptr_addr = rdev->wb.gpu_addr + R600_WB_UVD_RPTR_OFFSET;
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if (upper_32_bits(rptr_addr) != upper_32_bits(ring->gpu_addr)) {
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DRM_ERROR("UVD ring and rptr not in the same 4GB segment!\n");
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return -EINVAL;
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}
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/* force RBC into idle state */
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WREG32(UVD_RBC_RB_CNTL, 0x11010101);
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/* Set the write pointer delay */
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WREG32(UVD_RBC_RB_WPTR_CNTL, 0);
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/* set the wb address */
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WREG32(UVD_RBC_RB_RPTR_ADDR, rptr_addr >> 2);
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/* programm the 4GB memory segment for rptr and ring buffer */
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WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(rptr_addr) |
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WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
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(0x7 << 16) | (0x1 << 31));
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/* Initialize the ring buffer's read and write pointers */
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@ -2662,7 +2669,7 @@ static int r600_uvd_rbc_start(struct radeon_device *rdev, bool ring_test)
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/* Set ring buffer size */
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rb_bufsz = drm_order(ring->ring_size);
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rb_bufsz = (0x1 << 8) | rb_bufsz;
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WREG32(UVD_RBC_RB_CNTL, rb_bufsz);
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WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
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if (ring_test) {
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ring->ready = true;
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@ -1027,7 +1027,6 @@ struct radeon_wb {
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#define R600_WB_DMA_RPTR_OFFSET 1792
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#define R600_WB_IH_WPTR_OFFSET 2048
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#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
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#define R600_WB_UVD_RPTR_OFFSET 2560
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#define R600_WB_EVENT_OFFSET 3072
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#define CIK_WB_CP1_WPTR_OFFSET 3328
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#define CIK_WB_CP2_WPTR_OFFSET 3584
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@ -1157,9 +1157,9 @@ static struct radeon_asic_ring rv770_uvd_ring = {
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.ring_test = &r600_uvd_ring_test,
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.ib_test = &r600_uvd_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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.get_rptr = &r600_uvd_get_rptr,
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.get_wptr = &r600_uvd_get_wptr,
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.set_wptr = &r600_uvd_set_wptr,
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};
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static struct radeon_asic rv770_asic = {
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@ -1593,9 +1593,9 @@ static struct radeon_asic_ring cayman_uvd_ring = {
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.ring_test = &r600_uvd_ring_test,
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.ib_test = &r600_uvd_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &radeon_ring_generic_get_rptr,
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.get_wptr = &radeon_ring_generic_get_wptr,
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.set_wptr = &radeon_ring_generic_set_wptr,
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.get_rptr = &r600_uvd_get_rptr,
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.get_wptr = &r600_uvd_get_wptr,
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.set_wptr = &r600_uvd_set_wptr,
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};
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static struct radeon_asic cayman_asic = {
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@ -424,6 +424,12 @@ void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rde
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struct seq_file *m);
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/* uvd */
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uint32_t r600_uvd_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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uint32_t r600_uvd_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void r600_uvd_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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int r600_uvd_init(struct radeon_device *rdev, bool ring_test);
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void r600_uvd_stop(struct radeon_device *rdev);
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int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
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@ -363,7 +363,7 @@ u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
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{
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u32 rptr;
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if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
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if (rdev->wb.enabled)
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rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
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else
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rptr = RREG32(ring->rptr_reg);
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@ -1923,8 +1923,7 @@ static int rv770_startup(struct radeon_device *rdev)
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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@ -6416,8 +6416,7 @@ static int si_startup(struct radeon_device *rdev)
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if (rdev->has_uvd) {
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ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
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if (ring->ring_size) {
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r = radeon_ring_init(rdev, ring, ring->ring_size,
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R600_WB_UVD_RPTR_OFFSET,
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
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0, 0xfffff, RADEON_CP_PACKET2);
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if (!r)
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