x86: make x86_32 use tlb_64.c
Impact: less contention when issuing invalidate IPI, cleanup Make x86_32 use the same tlb code as 64bit. The 64bit code uses multiple IPI vectors for tlb shootdown to reduce contention. This patch makes x86_32 allocate the same 8 IPIs as x86_64 and share the code paths. Note that the usage of asmlinkage is inconsistent for x86_32 and 64 and calls for further cleanup. This has been noted with a FIXME comment in tlb_64.c. Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Tejun Heo
Родитель
6dd01bedee
Коммит
02cf94c370
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@ -58,8 +58,11 @@
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# define CALL_FUNCTION_VECTOR 0xfc
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# define CALL_FUNCTION_SINGLE_VECTOR 0xfb
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# define THERMAL_APIC_VECTOR 0xfa
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/* 0xf1 - 0xf9 : free */
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# define INVALIDATE_TLB_VECTOR 0xf0
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/* 0xf8 - 0xf9 : free */
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# define INVALIDATE_TLB_VECTOR_END 0xf7
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# define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
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# define NUM_INVALIDATE_TLB_VECTORS 8
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#else
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@ -11,10 +11,26 @@
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*/
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#ifdef CONFIG_X86_SMP
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BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
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BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
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BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
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BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
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BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
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BUILD_INTERRUPT3(invalidate_interrupt0,INVALIDATE_TLB_VECTOR_START+0,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt1,INVALIDATE_TLB_VECTOR_START+1,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt2,INVALIDATE_TLB_VECTOR_START+2,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt3,INVALIDATE_TLB_VECTOR_START+3,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt4,INVALIDATE_TLB_VECTOR_START+4,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt5,INVALIDATE_TLB_VECTOR_START+5,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt6,INVALIDATE_TLB_VECTOR_START+6,
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smp_invalidate_interrupt)
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BUILD_INTERRUPT3(invalidate_interrupt7,INVALIDATE_TLB_VECTOR_START+7,
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smp_invalidate_interrupt)
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#endif
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/*
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@ -58,7 +58,7 @@ obj-$(CONFIG_PCI) += early-quirks.o
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apm-y := apm_32.o
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obj-$(CONFIG_APM) += apm.o
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obj-$(CONFIG_X86_SMP) += smp.o
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obj-$(CONFIG_X86_SMP) += smpboot.o tsc_sync.o ipi.o tlb_$(BITS).o
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obj-$(CONFIG_X86_SMP) += smpboot.o tsc_sync.o ipi.o tlb_64.o
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obj-$(CONFIG_X86_32_SMP) += smpcommon.o
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obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o
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obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
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@ -672,7 +672,7 @@ common_interrupt:
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ENDPROC(common_interrupt)
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CFI_ENDPROC
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#define BUILD_INTERRUPT(name, nr) \
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#define BUILD_INTERRUPT3(name, nr, fn) \
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ENTRY(name) \
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RING0_INT_FRAME; \
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pushl $~(nr); \
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@ -680,11 +680,13 @@ ENTRY(name) \
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SAVE_ALL; \
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TRACE_IRQS_OFF \
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movl %esp,%eax; \
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call smp_##name; \
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call fn; \
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jmp ret_from_intr; \
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CFI_ENDPROC; \
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ENDPROC(name)
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#define BUILD_INTERRUPT(name, nr) BUILD_INTERRUPT3(name, nr, smp_##name)
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/* The include is where all of the SMP etc. interrupts come from */
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#include "entry_arch.h"
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@ -149,8 +149,15 @@ void __init native_init_IRQ(void)
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*/
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alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
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/* IPI for invalidation */
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alloc_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
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/* IPIs for invalidation */
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
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/* IPI for generic function call */
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alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
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@ -1,239 +0,0 @@
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#include <linux/spinlock.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <asm/tlbflush.h>
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DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
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= { &init_mm, 0, };
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/* must come after the send_IPI functions above for inlining */
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#include <mach_ipi.h>
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/*
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* Smarter SMP flushing macros.
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* c/o Linus Torvalds.
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*
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* These mean you can really definitely utterly forget about
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* writing to user space from interrupts. (Its not allowed anyway).
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*
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* Optimizations Manfred Spraul <manfred@colorfullife.com>
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*/
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static cpumask_var_t flush_cpumask;
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static struct mm_struct *flush_mm;
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static unsigned long flush_va;
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static DEFINE_SPINLOCK(tlbstate_lock);
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/*
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* We cannot call mmdrop() because we are in interrupt context,
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* instead update mm->cpu_vm_mask.
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*
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* We need to reload %cr3 since the page tables may be going
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* away from under us..
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*/
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void leave_mm(int cpu)
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{
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BUG_ON(percpu_read(cpu_tlbstate.state) == TLBSTATE_OK);
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cpu_clear(cpu, percpu_read(cpu_tlbstate.active_mm)->cpu_vm_mask);
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load_cr3(swapper_pg_dir);
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}
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EXPORT_SYMBOL_GPL(leave_mm);
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/*
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*
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* The flush IPI assumes that a thread switch happens in this order:
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* [cpu0: the cpu that switches]
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* 1) switch_mm() either 1a) or 1b)
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* 1a) thread switch to a different mm
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* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
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* Stop ipi delivery for the old mm. This is not synchronized with
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* the other cpus, but smp_invalidate_interrupt ignore flush ipis
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* for the wrong mm, and in the worst case we perform a superfluous
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* tlb flush.
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* 1a2) set cpu_tlbstate to TLBSTATE_OK
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* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
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* was in lazy tlb mode.
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* 1a3) update cpu_tlbstate[].active_mm
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* Now cpu0 accepts tlb flushes for the new mm.
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* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
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* Now the other cpus will send tlb flush ipis.
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* 1a4) change cr3.
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* 1b) thread switch without mm change
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* cpu_tlbstate[].active_mm is correct, cpu0 already handles
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* flush ipis.
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* 1b1) set cpu_tlbstate to TLBSTATE_OK
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* 1b2) test_and_set the cpu bit in cpu_vm_mask.
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* Atomically set the bit [other cpus will start sending flush ipis],
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* and test the bit.
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* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
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* 2) switch %%esp, ie current
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*
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* The interrupt must handle 2 special cases:
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* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
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* - the cpu performs speculative tlb reads, i.e. even if the cpu only
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* runs in kernel space, the cpu could load tlb entries for user space
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* pages.
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*
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* The good news is that cpu_tlbstate is local to each cpu, no
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* write/read ordering problems.
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*/
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/*
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* TLB flush IPI:
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*
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* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
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* 2) Leave the mm if we are in the lazy tlb mode.
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*
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* Interrupts are disabled.
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*/
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void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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unsigned int cpu;
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cpu = smp_processor_id();
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if (!cpumask_test_cpu(cpu, flush_cpumask))
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goto out;
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/*
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* This was a BUG() but until someone can quote me the
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* line from the intel manual that guarantees an IPI to
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* multiple CPUs is retried _only_ on the erroring CPUs
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* its staying as a return
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*
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* BUG();
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*/
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if (flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
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if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
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if (flush_va == TLB_FLUSH_ALL)
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local_flush_tlb();
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else
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__flush_tlb_one(flush_va);
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} else
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leave_mm(cpu);
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}
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out:
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ack_APIC_irq();
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smp_mb__before_clear_bit();
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cpumask_clear_cpu(cpu, flush_cpumask);
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smp_mb__after_clear_bit();
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inc_irq_stat(irq_tlb_count);
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}
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void native_flush_tlb_others(const struct cpumask *cpumask,
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struct mm_struct *mm, unsigned long va)
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{
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/*
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* - mask must exist :)
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*/
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BUG_ON(cpumask_empty(cpumask));
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BUG_ON(!mm);
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/*
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* i'm not happy about this global shared spinlock in the
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* MM hot path, but we'll see how contended it is.
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* AK: x86-64 has a faster method that could be ported.
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*/
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spin_lock(&tlbstate_lock);
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cpumask_andnot(flush_cpumask, cpumask, cpumask_of(smp_processor_id()));
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#ifdef CONFIG_HOTPLUG_CPU
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/* If a CPU which we ran on has gone down, OK. */
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cpumask_and(flush_cpumask, flush_cpumask, cpu_online_mask);
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if (unlikely(cpumask_empty(flush_cpumask))) {
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spin_unlock(&tlbstate_lock);
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return;
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}
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#endif
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flush_mm = mm;
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flush_va = va;
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/*
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* Make the above memory operations globally visible before
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* sending the IPI.
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*/
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smp_mb();
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/*
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* We have to send the IPI only to
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* CPUs affected.
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*/
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send_IPI_mask(flush_cpumask, INVALIDATE_TLB_VECTOR);
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while (!cpumask_empty(flush_cpumask))
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/* nothing. lockup detection does not belong here */
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cpu_relax();
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flush_mm = NULL;
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flush_va = 0;
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spin_unlock(&tlbstate_lock);
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}
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void flush_tlb_current_task(void)
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{
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struct mm_struct *mm = current->mm;
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preempt_disable();
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local_flush_tlb();
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if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
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flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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preempt_disable();
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if (current->active_mm == mm) {
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if (current->mm)
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local_flush_tlb();
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else
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leave_mm(smp_processor_id());
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}
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if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
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flush_tlb_others(&mm->cpu_vm_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
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{
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struct mm_struct *mm = vma->vm_mm;
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preempt_disable();
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if (current->active_mm == mm) {
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if (current->mm)
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__flush_tlb_one(va);
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else
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leave_mm(smp_processor_id());
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}
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if (cpumask_any_but(&mm->cpu_vm_mask, smp_processor_id()) < nr_cpu_ids)
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flush_tlb_others(&mm->cpu_vm_mask, mm, va);
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preempt_enable();
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}
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static void do_flush_tlb_all(void *info)
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{
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unsigned long cpu = smp_processor_id();
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__flush_tlb_all();
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if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
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leave_mm(cpu);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(do_flush_tlb_all, NULL, 1);
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}
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static int init_flush_cpumask(void)
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{
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alloc_cpumask_var(&flush_cpumask, GFP_KERNEL);
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return 0;
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}
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early_initcall(init_flush_cpumask);
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@ -113,7 +113,17 @@ EXPORT_SYMBOL_GPL(leave_mm);
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* Interrupts are disabled.
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*/
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asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
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/*
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* FIXME: use of asmlinkage is not consistent. On x86_64 it's noop
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* but still used for documentation purpose but the usage is slightly
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* inconsistent. On x86_32, asmlinkage is regparm(0) but interrupt
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* entry calls in with the first parameter in %eax. Maybe define
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* intrlinkage?
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*/
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#ifdef CONFIG_X86_64
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asmlinkage
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#endif
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void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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unsigned int cpu;
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unsigned int sender;
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