mtd: s3c2410: Merge plat/regs-nand.h into s3c2410.c
plat/regs-nand.h is used only by S3C2410 nand driver. Since there are no other users, merge this file into the driver code to remove platform dependency. While at it also remove unused macros. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Sachin Kamat
Brian Norris
Родитель
0a8899b31a
Коммит
02d018625b
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/* arch/arm/mach-s3c2410/include/mach/regs-nand.h
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*
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* Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 NAND register definitions
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*/
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#ifndef __ASM_ARM_REGS_NAND
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#define __ASM_ARM_REGS_NAND
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#define S3C2410_NFREG(x) (x)
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#define S3C2410_NFCONF S3C2410_NFREG(0x00)
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#define S3C2410_NFCMD S3C2410_NFREG(0x04)
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#define S3C2410_NFADDR S3C2410_NFREG(0x08)
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#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2440_NFCONT S3C2410_NFREG(0x04)
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#define S3C2440_NFCMD S3C2410_NFREG(0x08)
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#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
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#define S3C2440_NFDATA S3C2410_NFREG(0x10)
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#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
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#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
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#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
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#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
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#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
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#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
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#define S3C2440_NFSECC S3C2410_NFREG(0x34)
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#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
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#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
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#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
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#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
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#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
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#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
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#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
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#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
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#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
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#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_NFSTAT_BUSY (1<<0)
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#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
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#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
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#define S3C2440_NFCONF_ADVFLASH (1<<3)
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#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
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#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
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#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
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#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
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#define S3C2440_NFCONT_SOFTLOCK (1<<12)
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#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
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#define S3C2440_NFCONT_RNBINT_EN (1<<9)
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#define S3C2440_NFCONT_RN_FALLING (1<<8)
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#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
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#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
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#define S3C2440_NFCONT_INITECC (1<<4)
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#define S3C2440_NFCONT_nFCE (1<<1)
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#define S3C2440_NFCONT_ENABLE (1<<0)
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#define S3C2440_NFSTAT_READY (1<<0)
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#define S3C2440_NFSTAT_nCE (1<<1)
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#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
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#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
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#define S3C2412_NFCONF_NANDBOOT (1<<31)
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#define S3C2412_NFCONF_ECCCLKCON (1<<30)
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#define S3C2412_NFCONF_ECC_MLC (1<<24)
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#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
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#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
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#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
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#define S3C2412_NFCONT_SOFTLOCK (1<<16)
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#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
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#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
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#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
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#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
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#define S3C2412_NFCONT_nFCE1 (1<<2)
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#define S3C2412_NFCONT_nFCE0 (1<<1)
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#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
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#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
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#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
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#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
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#define S3C2412_NFSTAT_nFCE1 (1<<3)
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#define S3C2412_NFSTAT_nFCE0 (1<<2)
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#define S3C2412_NFSTAT_Res1 (1<<1)
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#define S3C2412_NFSTAT_READY (1<<0)
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#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
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#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
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#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
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#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
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#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
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#define S3C2412_NFECCERR_NONE (0)
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#define S3C2412_NFECCERR_1BIT (1)
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#define S3C2412_NFECCERR_MULTIBIT (2)
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#define S3C2412_NFECCERR_ECCAREA (3)
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#endif /* __ASM_ARM_REGS_NAND */
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@ -46,9 +46,43 @@
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/partitions.h>
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#include <plat/regs-nand.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#define S3C2410_NFREG(x) (x)
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#define S3C2410_NFCONF S3C2410_NFREG(0x00)
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#define S3C2410_NFCMD S3C2410_NFREG(0x04)
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#define S3C2410_NFADDR S3C2410_NFREG(0x08)
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#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
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#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
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#define S3C2410_NFECC S3C2410_NFREG(0x14)
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#define S3C2440_NFCONT S3C2410_NFREG(0x04)
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#define S3C2440_NFCMD S3C2410_NFREG(0x08)
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#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
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#define S3C2440_NFDATA S3C2410_NFREG(0x10)
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#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
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#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
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#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
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#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_NFSTAT_BUSY (1<<0)
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#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
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#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
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#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
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#define S3C2440_NFCONT_INITECC (1<<4)
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#define S3C2440_NFCONT_nFCE (1<<1)
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#define S3C2440_NFCONT_ENABLE (1<<0)
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#define S3C2440_NFSTAT_READY (1<<0)
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#define S3C2412_NFCONF_NANDBOOT (1<<31)
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#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
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#define S3C2412_NFCONT_nFCE0 (1<<1)
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#define S3C2412_NFSTAT_READY (1<<0)
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/* new oob placement block for use with hardware ecc generation
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/* new oob placement block for use with hardware ecc generation
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*/
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*/
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