clk: ti: Fix FAPLL parent enable bit handling
Commit 163152cbbe
("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.
This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Родитель
c517d838eb
Коммит
03208cc69f
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@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw)
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v |= (1 << FAPLL_MAIN_PLLEN);
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v |= FAPLL_MAIN_PLLEN;
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writel_relaxed(v, fd->base);
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return 0;
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@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw)
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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v &= ~(1 << FAPLL_MAIN_PLLEN);
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v &= ~FAPLL_MAIN_PLLEN;
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writel_relaxed(v, fd->base);
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}
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@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw)
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struct fapll_data *fd = to_fapll(hw);
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u32 v = readl_relaxed(fd->base);
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return v & (1 << FAPLL_MAIN_PLLEN);
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return v & FAPLL_MAIN_PLLEN;
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}
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static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,
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