PCI: mvebu: add I/O access wrappers
This change adds wrapper functions for MMIO access to PCIe IP block. And some 8/16-bit access are replaced by 32-bit. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Seungwon Jeon
Jason Cooper
Родитель
9f352f0e6c
Коммит
032b4c0cc3
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@ -140,29 +140,39 @@ struct mvebu_pcie_port {
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size_t iowin_size;
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};
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static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
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{
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writel(val, port->base + reg);
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}
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static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
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{
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return readl(port->base + reg);
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}
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static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
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{
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return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
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return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
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}
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static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
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{
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u32 stat;
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stat = readl(port->base + PCIE_STAT_OFF);
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stat = mvebu_readl(port, PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_BUS;
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stat |= nr << 8;
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writel(stat, port->base + PCIE_STAT_OFF);
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mvebu_writel(port, stat, PCIE_STAT_OFF);
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}
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static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
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{
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u32 stat;
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stat = readl(port->base + PCIE_STAT_OFF);
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stat = mvebu_readl(port, PCIE_STAT_OFF);
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stat &= ~PCIE_STAT_DEV;
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stat |= nr << 16;
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writel(stat, port->base + PCIE_STAT_OFF);
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mvebu_writel(port, stat, PCIE_STAT_OFF);
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}
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/*
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@ -180,33 +190,34 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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/* First, disable and clear BARs and windows. */
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for (i = 1; i < 3; i++) {
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writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
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writel(0, port->base + PCIE_BAR_LO_OFF(i));
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writel(0, port->base + PCIE_BAR_HI_OFF(i));
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mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
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mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
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mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
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}
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for (i = 0; i < 5; i++) {
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writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
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writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
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}
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writel(0, port->base + PCIE_WIN5_CTRL_OFF);
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writel(0, port->base + PCIE_WIN5_BASE_OFF);
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writel(0, port->base + PCIE_WIN5_REMAP_OFF);
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mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
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mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
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mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
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/* Setup windows for DDR banks. Count total DDR size on the fly. */
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000,
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port->base + PCIE_WIN04_BASE_OFF(i));
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writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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port->base + PCIE_WIN04_CTRL_OFF(i));
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mvebu_writel(port, cs->base & 0xffff0000,
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PCIE_WIN04_BASE_OFF(i));
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mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
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mvebu_writel(port,
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((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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PCIE_WIN04_CTRL_OFF(i));
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size += cs->size;
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}
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@ -216,41 +227,40 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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size = 1 << fls(size);
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/* Setup BAR[1] to all DRAM banks. */
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writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
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writel(0, port->base + PCIE_BAR_HI_OFF(1));
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writel(((size - 1) & 0xffff0000) | 1,
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port->base + PCIE_BAR_CTRL_OFF(1));
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mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
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mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
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mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
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PCIE_BAR_CTRL_OFF(1));
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}
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static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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{
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u16 cmd;
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u32 mask;
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u32 cmd, mask;
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/* Point PCIe unit MBUS decode windows to DRAM space. */
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mvebu_pcie_setup_wins(port);
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/* Master + slave enable. */
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cmd = readw(port->base + PCIE_CMD_OFF);
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cmd = mvebu_readl(port, PCIE_CMD_OFF);
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cmd |= PCI_COMMAND_IO;
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cmd |= PCI_COMMAND_MEMORY;
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cmd |= PCI_COMMAND_MASTER;
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writew(cmd, port->base + PCIE_CMD_OFF);
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mvebu_writel(port, cmd, PCIE_CMD_OFF);
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/* Enable interrupt lines A-D. */
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mask = readl(port->base + PCIE_MASK_OFF);
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mask = mvebu_readl(port, PCIE_MASK_OFF);
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mask |= PCIE_MASK_ENABLE_INTS;
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writel(mask, port->base + PCIE_MASK_OFF);
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mvebu_writel(port, mask, PCIE_MASK_OFF);
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}
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static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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writel(PCIE_CONF_ADDR(bus->number, devfn, where),
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port->base + PCIE_CONF_ADDR_OFF);
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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*val = readl(port->base + PCIE_CONF_DATA_OFF);
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*val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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@ -264,21 +274,24 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val)
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{
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int ret = PCIBIOS_SUCCESSFUL;
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u32 _val, shift = 8 * (where & 3);
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writel(PCIE_CONF_ADDR(bus->number, devfn, where),
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port->base + PCIE_CONF_ADDR_OFF);
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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_val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
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if (size == 4)
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writel(val, port->base + PCIE_CONF_DATA_OFF);
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_val = val;
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else if (size == 2)
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writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
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_val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
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else if (size == 1)
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writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
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_val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
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else
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ret = PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return ret;
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mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
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return PCIBIOS_SUCCESSFUL;
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}
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static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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