b43: add hardware tkip
This add hardware tkip for b43. Signed-off-by: Gregor Kowski <gregor.kowski@gmail.com> Acked-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
gregor kowski
John W. Linville
Родитель
11ba964d4f
Коммит
035d0243eb
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@ -1188,7 +1188,7 @@ static int dma_tx_fragment(struct b43_dmaring *ring,
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header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]);
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cookie = generate_cookie(ring, slot);
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err = b43_generate_txhdr(ring->dev, header,
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skb->data, skb->len, info, cookie);
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skb, info, cookie);
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if (unlikely(err)) {
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ring->current_slot = old_top_slot;
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ring->used_slots = old_used_slots;
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@ -80,6 +80,10 @@ static int modparam_nohwcrypt;
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module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
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static int modparam_hwtkip;
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module_param_named(hwtkip, modparam_hwtkip, int, 0444);
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MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
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static int modparam_qos = 1;
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module_param_named(qos, modparam_qos, int, 0444);
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MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
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@ -834,6 +838,85 @@ static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
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(index * 2) + 1, addrtmp[1]);
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}
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/* The ucode will use phase1 key with TEK key to decrypt rx packets.
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* When a packet is received, the iv32 is checked.
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* - if it doesn't the packet is returned without modification (and software
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* decryption can be done). That's what happen when iv16 wrap.
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* - if it does, the rc4 key is computed, and decryption is tried.
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* Either it will success and B43_RX_MAC_DEC is returned,
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* either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
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* and the packet is not usable (it got modified by the ucode).
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* So in order to never have B43_RX_MAC_DECERR, we should provide
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* a iv32 and phase1key that match. Because we drop packets in case of
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* B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
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* packets will be lost without higher layer knowing (ie no resync possible
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* until next wrap).
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*
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* NOTE : this should support 50 key like RCMTA because
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* (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
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*/
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static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
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u16 *phase1key)
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{
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unsigned int i;
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u32 offset;
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u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
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if (!modparam_hwtkip)
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return;
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if (b43_new_kidx_api(dev))
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pairwise_keys_start = B43_NR_GROUP_KEYS;
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B43_WARN_ON(index < pairwise_keys_start);
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/* We have four default TX keys and possibly four default RX keys.
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* Physical mac 0 is mapped to physical key 4 or 8, depending
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* on the firmware version.
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* So we must adjust the index here.
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*/
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index -= pairwise_keys_start;
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B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
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if (b43_debug(dev, B43_DBG_KEYS)) {
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b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
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index, iv32);
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}
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/* Write the key to the RX tkip shared mem */
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offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
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for (i = 0; i < 10; i += 2) {
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b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
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phase1key ? phase1key[i / 2] : 0);
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}
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b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
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b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
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}
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static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
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struct ieee80211_key_conf *keyconf, const u8 *addr,
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u32 iv32, u16 *phase1key)
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{
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struct b43_wl *wl = hw_to_b43_wl(hw);
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struct b43_wldev *dev;
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int index = keyconf->hw_key_idx;
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if (B43_WARN_ON(!modparam_hwtkip))
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return;
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mutex_lock(&wl->mutex);
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dev = wl->current_dev;
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if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
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goto out_unlock;
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keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
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rx_tkip_phase1_write(dev, index, iv32, phase1key);
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keymac_write(dev, index, addr);
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out_unlock:
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mutex_unlock(&wl->mutex);
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}
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static void do_key_write(struct b43_wldev *dev,
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u8 index, u8 algorithm,
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const u8 *key, size_t key_len, const u8 *mac_addr)
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@ -849,6 +932,19 @@ static void do_key_write(struct b43_wldev *dev,
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if (index >= pairwise_keys_start)
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keymac_write(dev, index, NULL); /* First zero out mac. */
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if (algorithm == B43_SEC_ALGO_TKIP) {
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/*
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* We should provide an initial iv32, phase1key pair.
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* We could start with iv32=0 and compute the corresponding
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* phase1key, but this means calling ieee80211_get_tkip_key
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* with a fake skb (or export other tkip function).
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* Because we are lazy we hope iv32 won't start with
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* 0xffffffff and let's b43_op_update_tkip_key provide a
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* correct pair.
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*/
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rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
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} else if (index >= pairwise_keys_start) /* clear it */
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rx_tkip_phase1_write(dev, index, 0, NULL);
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if (key)
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memcpy(buf, key, key_len);
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key_write(dev, index, algorithm, buf);
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@ -867,6 +963,15 @@ static int b43_key_write(struct b43_wldev *dev,
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int i;
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int pairwise_keys_start;
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/* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
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* - Temporal Encryption Key (128 bits)
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* - Temporal Authenticator Tx MIC Key (64 bits)
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* - Temporal Authenticator Rx MIC Key (64 bits)
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*
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* Hardware only store TEK
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*/
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if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
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key_len = 16;
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if (key_len > B43_SEC_KEYSIZE)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
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@ -973,6 +1078,14 @@ static void b43_dump_keymemory(struct b43_wldev *dev)
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printk(" Algo: %04X/%02X", algo, key->algorithm);
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if (index >= pairwise_keys_start) {
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if (key->algorithm == B43_SEC_ALGO_TKIP) {
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printk(" TKIP: ");
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offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
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for (i = 0; i < 14; i += 2) {
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u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
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printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
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}
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}
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rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
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((index - pairwise_keys_start) * 2) + 0);
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rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
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@ -3620,8 +3733,10 @@ static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
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switch (cmd) {
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case SET_KEY:
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if (algorithm == B43_SEC_ALGO_TKIP) {
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/* FIXME: No TKIP hardware encryption for now. */
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if (algorithm == B43_SEC_ALGO_TKIP &&
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(!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
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!modparam_hwtkip)) {
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/* We support only pairwise key */
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err = -EOPNOTSUPP;
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goto out_unlock;
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}
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@ -3651,6 +3766,8 @@ static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
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b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
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}
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
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if (algorithm == B43_SEC_ALGO_TKIP)
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key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
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break;
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case DISABLE_KEY: {
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err = b43_key_clear(dev, key->hw_key_idx);
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@ -4378,6 +4495,7 @@ static const struct ieee80211_ops b43_hw_ops = {
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.bss_info_changed = b43_op_bss_info_changed,
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.configure_filter = b43_op_configure_filter,
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.set_key = b43_op_set_key,
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.update_tkip_key = b43_op_update_tkip_key,
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.get_stats = b43_op_get_stats,
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.get_tx_stats = b43_op_get_tx_stats,
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.get_tsf = b43_op_get_tsf,
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@ -461,8 +461,8 @@ static int pio_tx_frame(struct b43_pio_txqueue *q,
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cookie = generate_cookie(q, pack);
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hdrlen = b43_txhdr_size(q->dev);
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err = b43_generate_txhdr(q->dev, (u8 *)&txhdr, skb->data,
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skb->len, info, cookie);
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err = b43_generate_txhdr(q->dev, (u8 *)&txhdr, skb,
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info, cookie);
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if (err)
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return err;
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@ -180,11 +180,12 @@ static u8 b43_calc_fallback_rate(u8 bitrate)
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/* Generate a TX data header. */
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int b43_generate_txhdr(struct b43_wldev *dev,
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u8 *_txhdr,
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const unsigned char *fragment_data,
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unsigned int fragment_len,
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struct sk_buff *skb_frag,
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struct ieee80211_tx_info *info,
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u16 cookie)
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{
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const unsigned char *fragment_data = skb_frag->data;
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unsigned int fragment_len = skb_frag->len;
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struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr;
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const struct b43_phy *phy = &dev->phy;
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const struct ieee80211_hdr *wlhdr =
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@ -258,9 +259,26 @@ int b43_generate_txhdr(struct b43_wldev *dev,
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mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) &
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B43_TXH_MAC_KEYALG;
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wlhdr_len = ieee80211_hdrlen(fctl);
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iv_len = min((size_t) info->control.hw_key->iv_len,
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ARRAY_SIZE(txhdr->iv));
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memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
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if (key->algorithm == B43_SEC_ALGO_TKIP) {
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u16 phase1key[5];
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int i;
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/* we give the phase1key and iv16 here, the key is stored in
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* shm. With that the hardware can do phase 2 and encryption.
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*/
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ieee80211_get_tkip_key(info->control.hw_key, skb_frag,
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IEEE80211_TKIP_P1_KEY, (u8*)phase1key);
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/* phase1key is in host endian */
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for (i = 0; i < 5; i++)
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phase1key[i] = cpu_to_le16(phase1key[i]);
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memcpy(txhdr->iv, phase1key, 10);
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/* iv16 */
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memcpy(txhdr->iv + 10, ((u8 *) wlhdr) + wlhdr_len, 3);
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} else {
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iv_len = min((size_t) info->control.hw_key->iv_len,
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ARRAY_SIZE(txhdr->iv));
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memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
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}
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}
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if (b43_is_old_txhdr_format(dev)) {
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b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->old_format.plcp),
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@ -176,8 +176,7 @@ size_t b43_txhdr_size(struct b43_wldev *dev)
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int b43_generate_txhdr(struct b43_wldev *dev,
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u8 * txhdr,
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const unsigned char *fragment_data,
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unsigned int fragment_len,
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struct sk_buff *skb_frag,
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struct ieee80211_tx_info *txctl, u16 cookie);
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/* Transmit Status */
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