sparc64: Add SPARC-T4 perf event support.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Родитель
7a37a0b8f8
Коммит
035ea28dde
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@ -53,8 +53,8 @@
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* normal code.
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*/
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#define MAX_HWEVENTS 2
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#define MAX_PCRS 1
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#define MAX_HWEVENTS 4
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#define MAX_PCRS 4
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#define MAX_PERIOD ((1UL << 32) - 1)
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#define PIC_UPPER_INDEX 0
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@ -597,6 +597,187 @@ static const struct sparc_pmu niagara2_pmu = {
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.num_pic_regs = 1,
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};
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static const struct perf_event_map niagara4_perfmon_event_map[] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
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[PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
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[PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
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[PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
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[PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
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};
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static const struct perf_event_map *niagara4_event_map(int event_id)
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{
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return &niagara4_perfmon_event_map[event_id];
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}
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static const cache_map_t niagara4_cache_map = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
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[C(RESULT_MISS)] = { (16 << 6) | 0x07 },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
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[C(RESULT_MISS)] = { (16 << 6) | 0x07 },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
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[C(RESULT_MISS)] = { (11 << 6) | 0x03 },
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
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[ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
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[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
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[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS)] = { (17 << 6) | 0x3f },
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS)] = { (6 << 6) | 0x3f },
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
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[C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
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[ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
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},
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},
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};
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static u32 sparc_vt_read_pmc(int idx)
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{
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u64 val = pcr_ops->read_pic(idx);
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return val & 0xffffffff;
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}
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static void sparc_vt_write_pmc(int idx, u64 val)
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{
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u64 pcr;
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/* There seems to be an internal latch on the overflow event
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* on SPARC-T4 that prevents it from triggering unless you
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* update the PIC exactly as we do here. The requirement
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* seems to be that you have to turn off event counting in the
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* PCR around the PIC update.
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*
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* For example, after the following sequence:
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*
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* 1) set PIC to -1
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* 2) enable event counting and overflow reporting in PCR
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* 3) overflow triggers, softint 15 handler invoked
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* 4) clear OV bit in PCR
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* 5) write PIC to -1
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*
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* a subsequent overflow event will not trigger. This
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* sequence works on SPARC-T3 and previous chips.
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*/
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pcr = pcr_ops->read_pcr(idx);
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pcr_ops->write_pcr(idx, PCR_N4_PICNPT);
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pcr_ops->write_pic(idx, val & 0xffffffff);
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pcr_ops->write_pcr(idx, pcr);
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}
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static const struct sparc_pmu niagara4_pmu = {
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.event_map = niagara4_event_map,
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.cache_map = &niagara4_cache_map,
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.max_events = ARRAY_SIZE(niagara4_perfmon_event_map),
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.read_pmc = sparc_vt_read_pmc,
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.write_pmc = sparc_vt_write_pmc,
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.upper_shift = 5,
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.lower_shift = 5,
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.event_mask = 0x7ff,
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.user_bit = PCR_N4_UTRACE,
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.priv_bit = PCR_N4_STRACE,
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/* We explicitly don't support hypervisor tracing. The T4
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* generates the overflow event for precise events via a trap
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* which will not be generated (ie. it's completely lost) if
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* we happen to be in the hypervisor when the event triggers.
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* Essentially, the overflow event reporting is completely
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* unusable when you have hypervisor mode tracing enabled.
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*/
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.hv_bit = 0,
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.irq_bit = PCR_N4_TOE,
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.upper_nop = 0,
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.lower_nop = 0,
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.flags = 0,
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.max_hw_events = 4,
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.num_pcrs = 4,
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.num_pic_regs = 4,
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};
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static const struct sparc_pmu *sparc_pmu __read_mostly;
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static u64 event_encoding(u64 event_id, int idx)
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@ -1465,6 +1646,10 @@ static bool __init supported_pmu(void)
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sparc_pmu = &niagara2_pmu;
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return true;
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}
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if (!strcmp(sparc_pmu_type, "niagara4")) {
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sparc_pmu = &niagara4_pmu;
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return true;
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}
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return false;
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}
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