ASoC: stm32: sai: add h7 support
Add support of SAI on STM32H7 family. Signed-off-by: olivier moysan <olivier.moysan@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
olivier moysan
Mark Brown
Родитель
3861da5801
Коммит
03e78a242a
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@ -27,8 +27,17 @@
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#include "stm32_sai.h"
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static const struct stm32_sai_conf stm32_sai_conf_f4 = {
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.version = SAI_STM32F4,
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};
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static const struct stm32_sai_conf stm32_sai_conf_h7 = {
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.version = SAI_STM32H7,
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};
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static const struct of_device_id stm32_sai_ids[] = {
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{ .compatible = "st,stm32f4-sai", .data = (void *)SAI_STM32F4 },
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{ .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
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{ .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
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{}
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};
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@ -52,7 +61,7 @@ static int stm32_sai_probe(struct platform_device *pdev)
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of_id = of_match_device(stm32_sai_ids, &pdev->dev);
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if (of_id)
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sai->version = (enum stm32_sai_version)of_id->data;
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sai->conf = (struct stm32_sai_conf *)of_id->data;
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else
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return -EINVAL;
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@ -31,6 +31,10 @@
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#define STM_SAI_CLRFR_REGX 0x18
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#define STM_SAI_DR_REGX 0x1C
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/* Sub-block A registers, relative to sub-block A address */
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#define STM_SAI_PDMCR_REGX 0x40
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#define STM_SAI_PDMLY_REGX 0x44
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/******************** Bit definition for SAI_GCR register *******************/
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#define SAI_GCR_SYNCIN_SHIFT 0
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#define SAI_GCR_SYNCIN_MASK GENMASK(1, SAI_GCR_SYNCIN_SHIFT)
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@ -75,10 +79,11 @@
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#define SAI_XCR1_NODIV BIT(SAI_XCR1_NODIV_SHIFT)
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#define SAI_XCR1_MCKDIV_SHIFT 20
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#define SAI_XCR1_MCKDIV_WIDTH 4
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#define SAI_XCR1_MCKDIV_MASK GENMASK(24, SAI_XCR1_MCKDIV_SHIFT)
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#define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == SAI_STM32F4) ? 4 : 6)
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#define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\
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SAI_XCR1_MCKDIV_SHIFT)
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#define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT)
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#define SAI_XCR1_MCKDIV_MAX ((1 << SAI_XCR1_MCKDIV_WIDTH) - 1)
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#define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1)
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#define SAI_XCR1_OSR_SHIFT 26
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#define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
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@ -178,8 +183,65 @@
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#define SAI_XCLRFR_SHIFT 0
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#define SAI_XCLRFR_MASK GENMASK(6, SAI_XCLRFR_SHIFT)
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/****************** Bit definition for SAI_PDMCR register ******************/
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#define SAI_PDMCR_PDMEN BIT(0)
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#define SAI_PDMCR_MICNBR_SHIFT 4
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#define SAI_PDMCR_MICNBR_MASK GENMASK(5, SAI_PDMCR_MICNBR_SHIFT)
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#define SAI_PDMCR_MICNBR_SET(x) ((x) << SAI_PDMCR_MICNBR_SHIFT)
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#define SAI_PDMCR_CKEN1 BIT(8)
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#define SAI_PDMCR_CKEN2 BIT(9)
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#define SAI_PDMCR_CKEN3 BIT(10)
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#define SAI_PDMCR_CKEN4 BIT(11)
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/****************** Bit definition for (SAI_PDMDLY register ****************/
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#define SAI_PDMDLY_1L_SHIFT 0
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#define SAI_PDMDLY_1L_MASK GENMASK(2, SAI_PDMDLY_1L_SHIFT)
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#define SAI_PDMDLY_1L_WIDTH 3
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#define SAI_PDMDLY_1R_SHIFT 4
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#define SAI_PDMDLY_1R_MASK GENMASK(6, SAI_PDMDLY_1R_SHIFT)
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#define SAI_PDMDLY_1R_WIDTH 3
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#define SAI_PDMDLY_2L_SHIFT 8
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#define SAI_PDMDLY_2L_MASK GENMASK(10, SAI_PDMDLY_2L_SHIFT)
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#define SAI_PDMDLY_2L_WIDTH 3
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#define SAI_PDMDLY_2R_SHIFT 12
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#define SAI_PDMDLY_2R_MASK GENMASK(14, SAI_PDMDLY_2R_SHIFT)
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#define SAI_PDMDLY_2R_WIDTH 3
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#define SAI_PDMDLY_3L_SHIFT 16
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#define SAI_PDMDLY_3L_MASK GENMASK(18, SAI_PDMDLY_3L_SHIFT)
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#define SAI_PDMDLY_3L_WIDTH 3
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#define SAI_PDMDLY_3R_SHIFT 20
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#define SAI_PDMDLY_3R_MASK GENMASK(22, SAI_PDMDLY_3R_SHIFT)
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#define SAI_PDMDLY_3R_WIDTH 3
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#define SAI_PDMDLY_4L_SHIFT 24
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#define SAI_PDMDLY_4L_MASK GENMASK(26, SAI_PDMDLY_4L_SHIFT)
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#define SAI_PDMDLY_4L_WIDTH 3
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#define SAI_PDMDLY_4R_SHIFT 28
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#define SAI_PDMDLY_4R_MASK GENMASK(30, SAI_PDMDLY_4R_SHIFT)
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#define SAI_PDMDLY_4R_WIDTH 3
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#define STM_SAI_IS_F4(ip) ((ip)->conf->version == SAI_STM32F4)
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#define STM_SAI_IS_H7(ip) ((ip)->conf->version == SAI_STM32H7)
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enum stm32_sai_version {
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SAI_STM32F4
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SAI_STM32F4,
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SAI_STM32H7
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};
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/**
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* struct stm32_sai_conf - SAI configuration
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* @version: SAI version
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*/
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struct stm32_sai_conf {
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int version;
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};
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/**
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@ -194,6 +256,6 @@ struct stm32_sai_data {
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struct platform_device *pdev;
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struct clk *clk_x8k;
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struct clk *clk_x11k;
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int version;
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struct stm32_sai_conf *conf;
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int irq;
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};
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@ -51,12 +51,15 @@
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#define STM_SAI_A_ID 0x0
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#define STM_SAI_B_ID 0x1
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#define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID)
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#define STM_SAI_IS_SUB_B(x) ((x)->id == STM_SAI_B_ID)
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#define STM_SAI_BLOCK_NAME(x) (((x)->id == STM_SAI_A_ID) ? "A" : "B")
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/**
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* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
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* @pdev: device data pointer
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* @regmap: SAI register map pointer
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* @regmap_config: SAI sub block register map configuration pointer
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* @dma_params: dma configuration data for rx or tx channel
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* @cpu_dai_drv: DAI driver data pointer
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* @cpu_dai: DAI runtime data pointer
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@ -79,6 +82,7 @@
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struct stm32_sai_sub_data {
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struct platform_device *pdev;
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struct regmap *regmap;
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const struct regmap_config *regmap_config;
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struct snd_dmaengine_dai_dma_data dma_params;
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struct snd_soc_dai_driver *cpu_dai_drv;
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struct snd_soc_dai *cpu_dai;
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@ -118,6 +122,8 @@ static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg)
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case STM_SAI_SR_REGX:
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case STM_SAI_CLRFR_REGX:
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case STM_SAI_DR_REGX:
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case STM_SAI_PDMCR_REGX:
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case STM_SAI_PDMLY_REGX:
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return true;
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default:
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return false;
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@ -145,13 +151,15 @@ static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg)
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case STM_SAI_SR_REGX:
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case STM_SAI_CLRFR_REGX:
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case STM_SAI_DR_REGX:
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case STM_SAI_PDMCR_REGX:
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case STM_SAI_PDMLY_REGX:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config stm32_sai_sub_regmap_config = {
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static const struct regmap_config stm32_sai_sub_regmap_config_f4 = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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@ -162,6 +170,17 @@ static const struct regmap_config stm32_sai_sub_regmap_config = {
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.fast_io = true,
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};
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static const struct regmap_config stm32_sai_sub_regmap_config_h7 = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = STM_SAI_PDMLY_REGX,
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.readable_reg = stm32_sai_sub_readable_reg,
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.volatile_reg = stm32_sai_sub_volatile_reg,
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.writeable_reg = stm32_sai_sub_writeable_reg,
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.fast_io = true,
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};
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static irqreturn_t stm32_sai_isr(int irq, void *devid)
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{
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struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
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@ -551,7 +570,8 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int cr1, mask, div = 0;
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int sai_clk_rate, ret;
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int sai_clk_rate, mclk_ratio, den, ret;
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int version = sai->pdata->conf->version;
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if (!sai->mclk_rate) {
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dev_err(cpu_dai->dev, "Mclk rate is null\n");
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@ -564,22 +584,54 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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clk_set_parent(sai->sai_ck, sai->pdata->clk_x8k);
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sai_clk_rate = clk_get_rate(sai->sai_ck);
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/*
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* mclk_rate = 256 * fs
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* MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
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* MCKDIV = sai_ck / (2 * mclk_rate) otherwise
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*/
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if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
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div = DIV_ROUND_CLOSEST(sai_clk_rate, 2 * sai->mclk_rate);
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if (STM_SAI_IS_F4(sai->pdata)) {
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/*
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* mclk_rate = 256 * fs
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* MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
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* MCKDIV = sai_ck / (2 * mclk_rate) otherwise
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*/
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if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
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div = DIV_ROUND_CLOSEST(sai_clk_rate,
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2 * sai->mclk_rate);
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} else {
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/*
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* TDM mode :
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* mclk on
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* MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0)
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* MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1)
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* mclk off
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* MCKDIV = sai_ck / (frl x ws) (NOMCK=1)
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* Note: NOMCK/NODIV correspond to same bit.
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*/
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if (sai->mclk_rate) {
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mclk_ratio = sai->mclk_rate / params_rate(params);
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if (mclk_ratio != 256) {
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if (mclk_ratio == 512) {
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mask = SAI_XCR1_OSR;
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cr1 = SAI_XCR1_OSR;
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} else {
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dev_err(cpu_dai->dev,
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"Wrong mclk ratio %d\n",
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mclk_ratio);
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return -EINVAL;
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}
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}
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div = DIV_ROUND_CLOSEST(sai_clk_rate, sai->mclk_rate);
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} else {
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/* mclk-fs not set, master clock not active. NOMCK=1 */
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den = sai->fs_length * params_rate(params);
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div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
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}
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}
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if (div > SAI_XCR1_MCKDIV_MAX) {
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if (div > SAI_XCR1_MCKDIV_MAX(version)) {
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dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
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return -EINVAL;
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}
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dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
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mask = SAI_XCR1_MCKDIV_MASK;
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cr1 = SAI_XCR1_MCKDIV_SET(div);
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mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
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cr1 = SAI_XCR1_MCKDIV_SET(div);
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
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if (ret < 0) {
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dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
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@ -780,8 +832,18 @@ static int stm32_sai_sub_parse_of(struct platform_device *pdev,
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return PTR_ERR(base);
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sai->phys_addr = res->start;
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sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", base,
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&stm32_sai_sub_regmap_config);
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sai->regmap_config = &stm32_sai_sub_regmap_config_f4;
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/* Note: PDM registers not available for H7 sub-block B */
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if (STM_SAI_IS_H7(sai->pdata) && STM_SAI_IS_SUB_A(sai))
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sai->regmap_config = &stm32_sai_sub_regmap_config_h7;
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sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck",
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base, sai->regmap_config);
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if (IS_ERR(sai->regmap)) {
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dev_err(&pdev->dev, "Failed to initialize MMIO\n");
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return PTR_ERR(sai->regmap);
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}
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/* Get direction property */
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if (of_property_match_string(np, "dma-names", "tx") >= 0) {
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