RISC-V: Parse cpu topology during boot.
Currently, there are no topology defined for RISC-V. Parse the cpu-map node from device tree and setup the cpu topology. CPU topology after applying the patch. $cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/core_siblings_list 0-3 $cat /sys/devices/system/cpu/cpu3/topology/physical_package_id 0 $cat /sys/devices/system/cpu/cpu3/topology/core_id 3 Signed-off-by: Atish Patra <atish.patra@wdc.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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@ -48,6 +48,7 @@ config RISCV
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select PCI_MSI if PCI
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select RISCV_TIMER
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select GENERIC_IRQ_MULTI_HANDLER
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select GENERIC_ARCH_TOPOLOGY if SMP
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select ARCH_HAS_PTE_SPECIAL
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select ARCH_HAS_MMIOWB
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select HAVE_EBPF_JIT if 64BIT
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@ -8,6 +8,7 @@
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/arch_topology.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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@ -35,6 +36,7 @@ static DECLARE_COMPLETION(cpu_running);
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void __init smp_prepare_boot_cpu(void)
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{
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init_cpu_topology();
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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@ -138,6 +140,7 @@ asmlinkage void __init smp_callin(void)
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trap_init();
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notify_cpu_starting(smp_processor_id());
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update_siblings_masks(smp_processor_id());
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set_cpu_online(smp_processor_id(), 1);
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/*
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* Remote TLB flushes are ignored while the CPU is offline, so emit
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