KVM: PPC: Book3S: Allow XICS emulation to work in nested hosts using XIVE
Currently, the KVM code assumes that if the host kernel is using the XIVE interrupt controller (the new interrupt controller that first appeared in POWER9 systems), then the in-kernel XICS emulation will use the XIVE hardware to deliver interrupts to the guest. However, this only works when the host is running in hypervisor mode and has full access to all of the XIVE functionality. It doesn't work in any nested virtualization scenario, either with PR KVM or nested-HV KVM, because the XICS-on-XIVE code calls directly into the native-XIVE routines, which are not initialized and cannot function correctly because they use OPAL calls, and OPAL is not available in a guest. This means that using the in-kernel XICS emulation in a nested hypervisor that is using XIVE as its interrupt controller will cause a (nested) host kernel crash. To fix this, we change most of the places where the current code calls xive_enabled() to select between the XICS-on-XIVE emulation and the plain XICS emulation to call a new function, xics_on_xive(), which returns false in a guest. However, there is a further twist. The plain XICS emulation has some functions which are used in real mode and access the underlying XICS controller (the interrupt controller of the host) directly. In the case of a nested hypervisor, this means doing XICS hypercalls directly. When the nested host is using XIVE as its interrupt controller, these hypercalls will fail. Therefore this also adds checks in the places where the XICS emulation wants to access the underlying interrupt controller directly, and if that is XIVE, makes the code use the virtual mode fallback paths, which call generic kernel infrastructure rather than doing direct XICS access. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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@ -36,6 +36,8 @@
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#endif
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#include <asm/paca.h>
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#include <asm/xive.h>
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#include <asm/cpu_has_feature.h>
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#endif
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/*
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@ -616,6 +618,18 @@ static inline int kvmppc_xive_set_irq(struct kvm *kvm, int irq_source_id, u32 ir
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static inline void kvmppc_xive_push_vcpu(struct kvm_vcpu *vcpu) { }
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#endif /* CONFIG_KVM_XIVE */
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#ifdef CONFIG_PPC_POWERNV
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static inline bool xics_on_xive(void)
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{
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return xive_enabled() && cpu_has_feature(CPU_FTR_HVMODE);
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}
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#else
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static inline bool xics_on_xive(void)
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{
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return false;
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}
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#endif
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/*
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* Prototypes for functions called only from assembler code.
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* Having prototypes reduces sparse errors.
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@ -635,7 +635,7 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id,
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r = -ENXIO;
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break;
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}
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if (xive_enabled())
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if (xics_on_xive())
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*val = get_reg_val(id, kvmppc_xive_get_icp(vcpu));
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else
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*val = get_reg_val(id, kvmppc_xics_get_icp(vcpu));
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@ -708,7 +708,7 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id,
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r = -ENXIO;
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break;
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}
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if (xive_enabled())
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if (xics_on_xive())
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r = kvmppc_xive_set_icp(vcpu, set_reg_val(id, *val));
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else
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r = kvmppc_xics_set_icp(vcpu, set_reg_val(id, *val));
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@ -984,7 +984,7 @@ int kvmppc_book3s_hcall_implemented(struct kvm *kvm, unsigned long hcall)
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int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level,
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bool line_status)
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{
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if (xive_enabled())
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if (xics_on_xive())
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return kvmppc_xive_set_irq(kvm, irq_source_id, irq, level,
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line_status);
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else
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@ -1037,7 +1037,7 @@ static int kvmppc_book3s_init(void)
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#ifdef CONFIG_KVM_XICS
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#ifdef CONFIG_KVM_XIVE
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if (xive_enabled()) {
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if (xics_on_xive()) {
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kvmppc_xive_init_module();
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kvm_register_device_ops(&kvm_xive_ops, KVM_DEV_TYPE_XICS);
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} else
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@ -1050,7 +1050,7 @@ static int kvmppc_book3s_init(void)
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static void kvmppc_book3s_exit(void)
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{
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#ifdef CONFIG_KVM_XICS
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if (xive_enabled())
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if (xics_on_xive())
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kvmppc_xive_exit_module();
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#endif
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#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
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@ -922,7 +922,7 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
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case H_IPOLL:
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case H_XIRR_X:
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if (kvmppc_xics_enabled(vcpu)) {
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if (xive_enabled()) {
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if (xics_on_xive()) {
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ret = H_NOT_AVAILABLE;
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return RESUME_GUEST;
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}
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@ -1431,7 +1431,7 @@ static int kvmppc_handle_nested_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
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case BOOK3S_INTERRUPT_HV_RM_HARD:
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vcpu->arch.trap = 0;
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r = RESUME_GUEST;
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if (!xive_enabled())
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if (!xics_on_xive())
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kvmppc_xics_rm_complete(vcpu, 0);
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break;
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default:
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@ -3649,7 +3649,7 @@ static void shrink_halt_poll_ns(struct kvmppc_vcore *vc)
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#ifdef CONFIG_KVM_XICS
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static inline bool xive_interrupt_pending(struct kvm_vcpu *vcpu)
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{
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if (!xive_enabled())
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if (!xics_on_xive())
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return false;
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return vcpu->arch.irq_pending || vcpu->arch.xive_saved_state.pipr <
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vcpu->arch.xive_saved_state.cppr;
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@ -4209,7 +4209,7 @@ static int kvmppc_vcpu_run_hv(struct kvm_run *run, struct kvm_vcpu *vcpu)
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vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
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srcu_read_unlock(&kvm->srcu, srcu_idx);
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} else if (r == RESUME_PASSTHROUGH) {
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if (WARN_ON(xive_enabled()))
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if (WARN_ON(xics_on_xive()))
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r = H_SUCCESS;
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else
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r = kvmppc_xics_rm_complete(vcpu, 0);
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@ -4733,7 +4733,7 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
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* If xive is enabled, we route 0x500 interrupts directly
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* to the guest.
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*/
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if (xive_enabled())
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if (xics_on_xive())
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lpcr |= LPCR_LPES;
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}
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@ -4969,7 +4969,7 @@ static int kvmppc_set_passthru_irq(struct kvm *kvm, int host_irq, int guest_gsi)
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if (i == pimap->n_mapped)
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pimap->n_mapped++;
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_set_mapped(kvm, guest_gsi, desc);
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else
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kvmppc_xics_set_mapped(kvm, guest_gsi, desc->irq_data.hwirq);
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@ -5010,7 +5010,7 @@ static int kvmppc_clr_passthru_irq(struct kvm *kvm, int host_irq, int guest_gsi)
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return -ENODEV;
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}
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_clr_mapped(kvm, guest_gsi, pimap->mapped[i].desc);
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else
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kvmppc_xics_clr_mapped(kvm, guest_gsi, pimap->mapped[i].r_hwirq);
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@ -5387,7 +5387,7 @@ static int kvmppc_book3s_init_hv(void)
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* indirectly, via OPAL.
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*/
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#ifdef CONFIG_SMP
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if (!xive_enabled() && !kvmhv_on_pseries() &&
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if (!xics_on_xive() && !kvmhv_on_pseries() &&
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!local_paca->kvm_hstate.xics_phys) {
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struct device_node *np;
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@ -257,7 +257,7 @@ void kvmhv_rm_send_ipi(int cpu)
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}
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/* We should never reach this */
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if (WARN_ON_ONCE(xive_enabled()))
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if (WARN_ON_ONCE(xics_on_xive()))
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return;
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/* Else poke the target with an IPI */
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@ -577,7 +577,7 @@ unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
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{
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_xirr(vcpu);
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if (unlikely(!__xive_vm_h_xirr))
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@ -592,7 +592,7 @@ unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu)
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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vcpu->arch.regs.gpr[5] = get_tb();
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_xirr(vcpu);
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if (unlikely(!__xive_vm_h_xirr))
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@ -606,7 +606,7 @@ unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
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{
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_ipoll(vcpu, server);
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if (unlikely(!__xive_vm_h_ipoll))
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{
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_ipi(vcpu, server, mfrr);
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if (unlikely(!__xive_vm_h_ipi))
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@ -635,7 +635,7 @@ int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
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{
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_cppr(vcpu, cppr);
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if (unlikely(!__xive_vm_h_cppr))
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{
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if (!kvmppc_xics_enabled(vcpu))
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return H_TOO_HARD;
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if (xive_enabled()) {
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if (xics_on_xive()) {
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if (is_rm())
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return xive_rm_h_eoi(vcpu, xirr);
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if (unlikely(!__xive_vm_h_eoi))
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@ -144,6 +144,13 @@ static void icp_rm_set_vcpu_irq(struct kvm_vcpu *vcpu,
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return;
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}
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if (xive_enabled() && kvmhv_on_pseries()) {
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/* No XICS access or hypercalls available, too hard */
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this_icp->rm_action |= XICS_RM_KICK_VCPU;
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this_icp->rm_kick_target = vcpu;
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return;
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}
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/*
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* Check if the core is loaded,
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* if not, find an available host core to post to wake the VCPU,
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server = be32_to_cpu(args->args[1]);
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priority = be32_to_cpu(args->args[2]);
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_set_xive(vcpu->kvm, irq, server, priority);
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else
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rc = kvmppc_xics_set_xive(vcpu->kvm, irq, server, priority);
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irq = be32_to_cpu(args->args[0]);
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server = priority = 0;
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_get_xive(vcpu->kvm, irq, &server, &priority);
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else
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rc = kvmppc_xics_get_xive(vcpu->kvm, irq, &server, &priority);
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@ -83,7 +83,7 @@ static void kvm_rtas_int_off(struct kvm_vcpu *vcpu, struct rtas_args *args)
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irq = be32_to_cpu(args->args[0]);
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_int_off(vcpu->kvm, irq);
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else
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rc = kvmppc_xics_int_off(vcpu->kvm, irq);
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@ -105,7 +105,7 @@ static void kvm_rtas_int_on(struct kvm_vcpu *vcpu, struct rtas_args *args)
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irq = be32_to_cpu(args->args[0]);
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if (xive_enabled())
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if (xics_on_xive())
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rc = kvmppc_xive_int_on(vcpu->kvm, irq);
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else
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rc = kvmppc_xics_int_on(vcpu->kvm, irq);
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@ -748,7 +748,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
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kvmppc_mpic_disconnect_vcpu(vcpu->arch.mpic, vcpu);
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break;
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case KVMPPC_IRQ_XICS:
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if (xive_enabled())
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if (xics_on_xive())
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kvmppc_xive_cleanup_vcpu(vcpu);
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else
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kvmppc_xics_free_icp(vcpu);
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@ -1931,7 +1931,7 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
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r = -EPERM;
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dev = kvm_device_from_filp(f.file);
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if (dev) {
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if (xive_enabled())
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if (xics_on_xive())
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r = kvmppc_xive_connect_vcpu(dev, vcpu, cap->args[1]);
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else
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r = kvmppc_xics_connect_vcpu(dev, vcpu, cap->args[1]);
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