MIPS: Reorganize ISA constants strictly as bitmasks.
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
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0401572a9b
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@ -116,6 +116,27 @@
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#endif
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#endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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# endif
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/*
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* Shortcuts ...
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*/
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#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
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#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
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#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
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#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
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#ifndef cpu_has_dsp
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#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
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#endif
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@ -144,18 +165,6 @@
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses 0
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# endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1 0
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2 0
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# endif
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#endif
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#ifdef CONFIG_64BIT
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@ -174,18 +183,6 @@
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# ifndef cpu_has_64bit_addresses
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# define cpu_has_64bit_addresses 1
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# endif
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# ifndef cpu_has_mips32r1
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# define cpu_has_mips32r1 0
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# endif
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# ifndef cpu_has_mips32r2
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# define cpu_has_mips32r2 0
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# endif
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# ifndef cpu_has_mips64r1
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# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
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# endif
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# ifndef cpu_has_mips64r2
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# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
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# endif
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#endif
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#ifdef CONFIG_CPU_MIPSR2
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@ -202,17 +202,20 @@
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* ISA Level encodings
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*
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*/
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#define MIPS_CPU_ISA_64BIT 0x00008000
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#define MIPS_CPU_ISA_I 0x00000001
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#define MIPS_CPU_ISA_II 0x00000002
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#define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_III 0x00000003
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#define MIPS_CPU_ISA_IV 0x00000004
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#define MIPS_CPU_ISA_V 0x00000005
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#define MIPS_CPU_ISA_M32R1 0x00000020
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#define MIPS_CPU_ISA_M32R2 0x00000040
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#define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT)
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#define MIPS_CPU_ISA_M64R1 0x00000080
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#define MIPS_CPU_ISA_M64R2 0x00000100
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#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
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MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
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#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
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MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
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/*
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* CPU Option encodings
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