ARM: OMAP: DMA: Remove __REG access
Remove __REG access in DMA code, use dma_read/write instead: - dynamically set the omap_dma_base based on the omap type - omap_read/write becomes dma_read/write - dma channel registers are read with dma_ch_read/write Cc: David Brownell <david-b@pacbell.net> Cc: linux-usb@vger.kernel.org Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
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4d96372e6d
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0499bdeb1d
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@ -491,32 +491,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req)
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/*-------------------------------------------------------------------------*/
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static inline dma_addr_t dma_csac(unsigned lch)
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{
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dma_addr_t csac;
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/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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csac = OMAP_DMA_CSAC_REG(lch);
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if (csac == 0)
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csac = OMAP_DMA_CSAC_REG(lch);
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return csac;
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}
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static inline dma_addr_t dma_cdac(unsigned lch)
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{
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dma_addr_t cdac;
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/* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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cdac = OMAP_DMA_CDAC_REG(lch);
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if (cdac == 0)
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cdac = OMAP_DMA_CDAC_REG(lch);
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return cdac;
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}
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static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
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{
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dma_addr_t end;
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@ -527,7 +501,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
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if (cpu_is_omap15xx())
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return 0;
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end = dma_csac(ep->lch);
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end = omap_get_dma_src_pos(ep->lch);
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if (end == ep->dma_counter)
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return 0;
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@ -537,15 +511,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
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return end - start;
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}
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#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
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? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
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: dma_cdac(x))
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static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
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{
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dma_addr_t end;
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end = DMA_DEST_LAST(ep->lch);
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end = omap_get_dma_dst_pos(ep->lch);
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if (end == ep->dma_counter)
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return 0;
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@ -596,7 +566,7 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
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0, 0);
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omap_start_dma(ep->lch);
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ep->dma_counter = dma_csac(ep->lch);
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ep->dma_counter = omap_get_dma_src_pos(ep->lch);
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UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
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UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
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req->dma_bytes = length;
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@ -654,7 +624,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
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omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
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OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
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0, 0);
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ep->dma_counter = DMA_DEST_LAST(ep->lch);
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ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
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UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
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UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
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@ -834,7 +804,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
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/* channel type P: hw synch (fifo) */
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if (cpu_class_is_omap1() && !cpu_is_omap15xx())
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OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
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omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
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}
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just_restart:
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@ -881,7 +851,7 @@ static void dma_channel_release(struct omap_ep *ep)
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else
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req = NULL;
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active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
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active = omap_get_dma_active_status(ep->lch);
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DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
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active ? "active" : "idle",
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@ -22,107 +22,128 @@
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#define __ASM_ARCH_DMA_H
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/* Hardware registers for omap1 */
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#define OMAP_DMA_BASE (0xfffed800)
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#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
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#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
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#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
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#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
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#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
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#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
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#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
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#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
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#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
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#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
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#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
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#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
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#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
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#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
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#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
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#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
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#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
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#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
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#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
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#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
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#define OMAP1_DMA_BASE (0xfffed800)
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/* Hardware registers for omap2 */
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#if defined(CONFIG_ARCH_OMAP3)
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#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)
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#else /* CONFIG_ARCH_OMAP2 */
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#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)
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#endif
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#define OMAP1_DMA_GCR 0x400
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#define OMAP1_DMA_GSCR 0x404
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#define OMAP1_DMA_GRST 0x408
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#define OMAP1_DMA_HW_ID 0x442
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#define OMAP1_DMA_PCH2_ID 0x444
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#define OMAP1_DMA_PCH0_ID 0x446
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#define OMAP1_DMA_PCH1_ID 0x448
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#define OMAP1_DMA_PCHG_ID 0x44a
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#define OMAP1_DMA_PCHD_ID 0x44c
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#define OMAP1_DMA_CAPS_0_U 0x44e
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#define OMAP1_DMA_CAPS_0_L 0x450
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#define OMAP1_DMA_CAPS_1_U 0x452
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#define OMAP1_DMA_CAPS_1_L 0x454
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#define OMAP1_DMA_CAPS_2 0x456
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#define OMAP1_DMA_CAPS_3 0x458
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#define OMAP1_DMA_CAPS_4 0x45a
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#define OMAP1_DMA_PCH2_SR 0x460
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#define OMAP1_DMA_PCH0_SR 0x480
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#define OMAP1_DMA_PCH1_SR 0x482
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#define OMAP1_DMA_PCHD_SR 0x4c0
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#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)
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#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)
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#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)
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#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)
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#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)
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#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)
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#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)
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#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)
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#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)
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#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)
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#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)
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#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)
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#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)
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#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)
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#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
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#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
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/* Hardware registers for omap2 and omap3 */
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#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
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#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
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#define OMAP_DMA4_REVISION 0x00
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#define OMAP_DMA4_GCR 0x78
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#define OMAP_DMA4_IRQSTATUS_L0 0x08
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#define OMAP_DMA4_IRQSTATUS_L1 0x0c
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#define OMAP_DMA4_IRQSTATUS_L2 0x10
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#define OMAP_DMA4_IRQSTATUS_L3 0x14
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#define OMAP_DMA4_IRQENABLE_L0 0x18
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#define OMAP_DMA4_IRQENABLE_L1 0x1c
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#define OMAP_DMA4_IRQENABLE_L2 0x20
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#define OMAP_DMA4_IRQENABLE_L3 0x24
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#define OMAP_DMA4_SYSSTATUS 0x28
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#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
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#define OMAP_DMA4_CAPS_0 0x64
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#define OMAP_DMA4_CAPS_2 0x6c
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#define OMAP_DMA4_CAPS_3 0x70
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#define OMAP_DMA4_CAPS_4 0x74
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
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#ifdef CONFIG_ARCH_OMAP1
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/* Common channel specific registers for omap1 */
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#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
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#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
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#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
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#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
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#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
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#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
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#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
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#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
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#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
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#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
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#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
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#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
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#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
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#else
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#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
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#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
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#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
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#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
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#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
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#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
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#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
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#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
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#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
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#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
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#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
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#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
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#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
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#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
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#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
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/* Common channel specific registers for omap2 */
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#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
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#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
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#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
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#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
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#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
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#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
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#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
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#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
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#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
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#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
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#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
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#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
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#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
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#endif
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#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
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#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
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#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
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#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
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#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
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#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
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#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
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#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
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#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
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#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
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#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
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#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
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#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
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#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
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/* Channel specific registers only on omap1 */
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#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
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#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
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#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
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#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
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#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
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#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
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#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
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#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
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#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
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#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
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#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
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#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
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#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
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#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
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#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
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#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
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#define OMAP1_DMA_CCEN(n) 0
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#define OMAP1_DMA_CCFN(n) 0
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/* Channel specific registers only on omap2 */
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#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
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#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
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#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
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#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
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#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
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#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
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#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
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#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
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#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
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#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
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/* Dummy defines to keep multi-omap compiles happy */
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#define OMAP1_DMA_REVISION 0
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#define OMAP1_DMA_IRQSTATUS_L0 0
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#define OMAP1_DMA_IRQENABLE_L0 0
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||||
#define OMAP1_DMA_OCP_SYSCONFIG 0
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#define OMAP_DMA4_HW_ID 0
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#define OMAP_DMA4_CAPS_0_L 0
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#define OMAP_DMA4_CAPS_0_U 0
|
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#define OMAP_DMA4_CAPS_1_L 0
|
||||
#define OMAP_DMA4_CAPS_1_U 0
|
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#define OMAP_DMA4_GSCR 0
|
||||
#define OMAP_DMA4_CPC(n) 0
|
||||
|
||||
#define OMAP_DMA4_LCH_CTRL(n) 0
|
||||
#define OMAP_DMA4_COLOR_L(n) 0
|
||||
#define OMAP_DMA4_COLOR_U(n) 0
|
||||
#define OMAP_DMA4_CCR2(n) 0
|
||||
#define OMAP1_DMA_CSSA(n) 0
|
||||
#define OMAP1_DMA_CDSA(n) 0
|
||||
#define OMAP_DMA4_CSSA_L(n) 0
|
||||
#define OMAP_DMA4_CSSA_U(n) 0
|
||||
#define OMAP_DMA4_CDSA_L(n) 0
|
||||
#define OMAP_DMA4_CDSA_U(n) 0
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
|
|
@ -369,6 +390,13 @@ enum omap_dma_write_mode {
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|||
OMAP_DMA_WRITE_LAST_NON_POSTED
|
||||
};
|
||||
|
||||
enum omap_dma_channel_mode {
|
||||
OMAP_DMA_LCH_2D = 0,
|
||||
OMAP_DMA_LCH_G,
|
||||
OMAP_DMA_LCH_P,
|
||||
OMAP_DMA_LCH_PD
|
||||
};
|
||||
|
||||
struct omap_dma_channel_params {
|
||||
int data_type; /* data type 8,16,32 */
|
||||
int elem_count; /* number of elements in a frame */
|
||||
|
|
@ -417,6 +445,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
|
|||
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
|
||||
u32 color);
|
||||
extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
|
||||
extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
|
||||
|
||||
extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
|
||||
unsigned long src_start,
|
||||
|
|
@ -447,6 +476,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch);
|
|||
extern dma_addr_t omap_get_dma_dst_pos(int lch);
|
||||
extern int omap_get_dma_src_addr_counter(int lch);
|
||||
extern void omap_clear_dma(int lch);
|
||||
extern int omap_get_dma_active_status(int lch);
|
||||
extern int omap_dma_running(void);
|
||||
extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
|
||||
int tparams);
|
||||
|
|
|
|||
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