arm64: dts: qcom: qcs404: Add CPR and populate OPP table
Add CPR and populate OPP table. Co-developed-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20191129213917.1301110-4-niklas.cassel@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Niklas Cassel
Bjorn Andersson
Родитель
cbccc6bcdf
Коммит
04aadcaadd
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@ -44,7 +44,8 @@
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&pms405_s3>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU1: cpu@101 {
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@ -57,7 +58,8 @@
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&pms405_s3>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU2: cpu@102 {
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@ -70,7 +72,8 @@
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&pms405_s3>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU3: cpu@103 {
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@ -83,7 +86,8 @@
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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cpu-supply = <&pms405_s3>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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L2_0: l2-cache {
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@ -107,20 +111,37 @@
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};
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cpu_opp_table: cpu-opp-table {
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compatible = "operating-points-v2";
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compatible = "operating-points-v2-kryo-cpu";
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opp-shared;
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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opp-microvolt = <1224000 1224000 1224000>;
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required-opps = <&cpr_opp1>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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opp-microvolt = <1288000 1288000 1288000>;
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required-opps = <&cpr_opp2>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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opp-microvolt = <1384000 1384000 1384000>;
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required-opps = <&cpr_opp3>;
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};
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};
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cpr_opp_table: cpr-opp-table {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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@ -310,6 +331,62 @@
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tsens_caldata: caldata@d0 {
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reg = <0x1f8 0x14>;
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};
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cpr_efuse_speedbin: speedbin@13c {
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reg = <0x13c 0x4>;
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bits = <2 3>;
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};
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cpr_efuse_quot_offset1: qoffset1@231 {
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reg = <0x231 0x4>;
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bits = <4 7>;
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};
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cpr_efuse_quot_offset2: qoffset2@232 {
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reg = <0x232 0x4>;
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bits = <3 7>;
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};
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cpr_efuse_quot_offset3: qoffset3@233 {
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reg = <0x233 0x4>;
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bits = <2 7>;
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};
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cpr_efuse_init_voltage1: ivoltage1@229 {
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reg = <0x229 0x4>;
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bits = <4 6>;
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};
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cpr_efuse_init_voltage2: ivoltage2@22a {
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reg = <0x22a 0x4>;
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bits = <2 6>;
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};
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cpr_efuse_init_voltage3: ivoltage3@22b {
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reg = <0x22b 0x4>;
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bits = <0 6>;
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};
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cpr_efuse_quot1: quot1@22b {
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reg = <0x22b 0x4>;
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bits = <6 12>;
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};
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cpr_efuse_quot2: quot2@22d {
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reg = <0x22d 0x4>;
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bits = <2 12>;
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};
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cpr_efuse_quot3: quot3@230 {
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reg = <0x230 0x4>;
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bits = <0 12>;
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};
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cpr_efuse_ring1: ring1@228 {
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reg = <0x228 0x4>;
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bits = <0 3>;
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};
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cpr_efuse_ring2: ring2@228 {
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reg = <0x228 0x4>;
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bits = <4 3>;
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};
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cpr_efuse_ring3: ring3@229 {
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reg = <0x229 0x4>;
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bits = <0 3>;
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};
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cpr_efuse_revision: revision@218 {
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reg = <0x218 0x4>;
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bits = <3 3>;
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};
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};
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rng: rng@e3000 {
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@ -952,6 +1029,45 @@
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clocks = <&sleep_clk>;
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};
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cpr: power-controller@b018000 {
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compatible = "qcom,qcs404-cpr", "qcom,cpr";
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reg = <0x0b018000 0x1000>;
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interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xo_board>;
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clock-names = "ref";
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vdd-apc-supply = <&pms405_s3>;
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#power-domain-cells = <0>;
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operating-points-v2 = <&cpr_opp_table>;
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acc-syscon = <&tcsr>;
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nvmem-cells = <&cpr_efuse_quot_offset1>,
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<&cpr_efuse_quot_offset2>,
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<&cpr_efuse_quot_offset3>,
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<&cpr_efuse_init_voltage1>,
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<&cpr_efuse_init_voltage2>,
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<&cpr_efuse_init_voltage3>,
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<&cpr_efuse_quot1>,
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<&cpr_efuse_quot2>,
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<&cpr_efuse_quot3>,
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<&cpr_efuse_ring1>,
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<&cpr_efuse_ring2>,
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<&cpr_efuse_ring3>,
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<&cpr_efuse_revision>;
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nvmem-cell-names = "cpr_quotient_offset1",
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"cpr_quotient_offset2",
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"cpr_quotient_offset3",
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"cpr_init_voltage1",
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"cpr_init_voltage2",
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"cpr_init_voltage3",
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"cpr_quotient1",
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"cpr_quotient2",
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"cpr_quotient3",
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"cpr_ring_osc1",
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"cpr_ring_osc2",
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"cpr_ring_osc3",
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"cpr_fuse_revision";
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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