ssb: update reject bit for Target State Low
My 14e4:4315 is SSB_IDLOW_SSBREV_26: read32 0xfaafcff8 -> 0x600422d5 My 14e4:4328 is SSB_IDLOW_SSBREV_24: read32 0xfaafcff8 -> 0x400422c5 My 14e4:432b is SSB_IDLOW_SSBREV_26 again: read32 0xfaafcff8 -> 0x600422d5 For all of them wl driver is using 0x2 reject bit: write32(0xf98) <- 0x00010002 So it seems SSB 2.3 is the exception using another bit. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1117,23 +1117,22 @@ static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
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{
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{
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u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
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u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
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/* The REJECT bit changed position in TMSLOW between
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/* The REJECT bit seems to be different for Backplane rev 2.3 */
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* Backplane revisions. */
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switch (rev) {
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switch (rev) {
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case SSB_IDLOW_SSBREV_22:
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case SSB_IDLOW_SSBREV_22:
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return SSB_TMSLOW_REJECT_22;
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case SSB_IDLOW_SSBREV_24:
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case SSB_IDLOW_SSBREV_26:
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return SSB_TMSLOW_REJECT;
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case SSB_IDLOW_SSBREV_23:
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case SSB_IDLOW_SSBREV_23:
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return SSB_TMSLOW_REJECT_23;
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return SSB_TMSLOW_REJECT_23;
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case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
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case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
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case SSB_IDLOW_SSBREV_25: /* same here */
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case SSB_IDLOW_SSBREV_26: /* same here */
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case SSB_IDLOW_SSBREV_27: /* same here */
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case SSB_IDLOW_SSBREV_27: /* same here */
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return SSB_TMSLOW_REJECT_23; /* this is a guess */
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return SSB_TMSLOW_REJECT; /* this is a guess */
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default:
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default:
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printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
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printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
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WARN_ON(1);
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WARN_ON(1);
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}
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}
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return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
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return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
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}
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}
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int ssb_device_is_enabled(struct ssb_device *dev)
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int ssb_device_is_enabled(struct ssb_device *dev)
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@ -97,7 +97,7 @@
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#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
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#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
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#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
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#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
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#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
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#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
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#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
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#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
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#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
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#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
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#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
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#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
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#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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