drivers/irqchip: Remove EZChip NPS interrupt controller
NPS platform has been removed from ARC port and there are no in-tree users of it now. So RIP ! Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20201105212210.1891598-3-vgupta@synopsys.com
This commit is contained in:
Vineet Gupta
Marc Zyngier
Родитель
b388fa5014
Коммит
04e7f423f4
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@ -387,13 +387,6 @@ config LS_SCFG_MSI
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config PARTITION_PERCPU
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bool
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config EZNPS_GIC
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bool "NPS400 Global Interrupt Manager (GIM)"
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depends on ARC || (COMPILE_TEST && !64BIT)
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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@ -86,7 +86,6 @@ obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
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obj-$(CONFIG_MVEBU_SEI) += irq-mvebu-sei.o
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obj-$(CONFIG_LS_EXTIRQ) += irq-ls-extirq.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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@ -1,165 +0,0 @@
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/*
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include <soc/nps/common.h>
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#define NPS_NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */
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#define NPS_TIMER0_IRQ 3
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/*
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* NPS400 core includes an Interrupt Controller (IC) support.
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* All cores can deactivate level irqs at first level control
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* at cores mesh layer called MTM.
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* For devices out side chip e.g. uart, network there is another
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* level called Global Interrupt Manager (GIM).
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* This second level can control level and edge interrupt.
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*
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* NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
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* with private HW copy per CPU.
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*/
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static void nps400_irq_mask(struct irq_data *irqd)
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{
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unsigned int ienb;
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unsigned int irq = irqd_to_hwirq(irqd);
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ienb = read_aux_reg(AUX_IENABLE);
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ienb &= ~(1 << irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static void nps400_irq_unmask(struct irq_data *irqd)
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{
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unsigned int ienb;
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unsigned int irq = irqd_to_hwirq(irqd);
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ienb = read_aux_reg(AUX_IENABLE);
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ienb |= (1 << irq);
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write_aux_reg(AUX_IENABLE, ienb);
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}
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static void nps400_irq_eoi_global(struct irq_data *irqd)
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{
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unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
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write_aux_reg(CTOP_AUX_IACK, 1 << irq);
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/* Don't ack GIC before all device access attempts are done */
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mb();
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nps_ack_gic();
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}
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static void nps400_irq_ack(struct irq_data *irqd)
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{
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unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
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write_aux_reg(CTOP_AUX_IACK, 1 << irq);
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}
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static struct irq_chip nps400_irq_chip_fasteoi = {
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.name = "NPS400 IC Global",
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.irq_mask = nps400_irq_mask,
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.irq_unmask = nps400_irq_unmask,
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.irq_eoi = nps400_irq_eoi_global,
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};
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static struct irq_chip nps400_irq_chip_percpu = {
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.name = "NPS400 IC",
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.irq_mask = nps400_irq_mask,
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.irq_unmask = nps400_irq_unmask,
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.irq_ack = nps400_irq_ack,
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};
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static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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switch (hw) {
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case NPS_TIMER0_IRQ:
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#ifdef CONFIG_SMP
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case NPS_IPI_IRQ:
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#endif
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irq_set_percpu_devid(virq);
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irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
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handle_percpu_devid_irq);
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break;
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default:
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irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
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handle_fasteoi_irq);
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break;
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}
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return 0;
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}
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static const struct irq_domain_ops nps400_irq_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = nps400_irq_map,
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};
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static int __init nps400_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *nps400_root_domain;
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if (parent) {
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pr_err("DeviceTree incore ic not a root irq controller\n");
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return -EINVAL;
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}
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nps400_root_domain = irq_domain_add_linear(node, NPS_NR_CPU_IRQS,
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&nps400_irq_ops, NULL);
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if (!nps400_root_domain) {
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pr_err("nps400 root irq domain not avail\n");
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return -ENOMEM;
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}
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/*
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* Needed for primary domain lookup to succeed
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* This is a primary irqchip, and can never have a parent
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*/
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irq_set_default_host(nps400_root_domain);
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#ifdef CONFIG_SMP
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irq_create_mapping(nps400_root_domain, NPS_IPI_IRQ);
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#endif
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return 0;
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}
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IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
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