Second Round of Renesas ARM Based SoC Clk Updates for v3.18

* Add r8a7740, sh73a0 SoCs to MSTP bindings
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Merge tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Second Round of Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman.

* Add r8a7740, sh73a0 SoCs to MSTP bindings

* tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings

Signed-off-by: Olof Johansson <olof@lixom.net>

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

@@ -11,9 +11,11 @@ Required Properties:
 
   - compatible: Must be one of the following
     - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
+    - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
     - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
     - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
     - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
   - reg: Base address and length of the I/O mapped registers used by the MSTP
     clocks. The first register is the clock control register and is mandatory.