mfd: Update abstract dbx500 interface
This prefixes a number of accessor functions with db8500_* since they are DB8500-specific and we need to move to this naming scheme. We also replace numerous instances of machine_is() with cpu_is() which covers the right type of ASICs rather than entire machines i.e. boards. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mattias Nilsson
Samuel Ortiz
Родитель
b58d12fe6c
Коммит
0508901ca7
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@ -884,23 +884,23 @@ int db8500_prcmu_get_arm_opp(void)
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}
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/**
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* prcmu_get_ddr_opp - get the current DDR OPP
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* db8500_prcmu_get_ddr_opp - get the current DDR OPP
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*
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* Returns: the current DDR OPP
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*/
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int prcmu_get_ddr_opp(void)
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int db8500_prcmu_get_ddr_opp(void)
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{
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return readb(PRCM_DDR_SUBSYS_APE_MINBW);
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}
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/**
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* set_ddr_opp - set the appropriate DDR OPP
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* db8500_set_ddr_opp - set the appropriate DDR OPP
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* @opp: The new DDR operating point to which transition is to be made
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* Returns: 0 on success, non-zero on failure
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*
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* This function sets the operating point of the DDR.
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*/
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int prcmu_set_ddr_opp(u8 opp)
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int db8500_prcmu_set_ddr_opp(u8 opp)
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{
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if (opp < DDR_100_OPP || opp > DDR_25_OPP)
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return -EINVAL;
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@ -911,13 +911,13 @@ int prcmu_set_ddr_opp(u8 opp)
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return 0;
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}
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/**
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* set_ape_opp - set the appropriate APE OPP
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* db8500_set_ape_opp - set the appropriate APE OPP
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* @opp: The new APE operating point to which transition is to be made
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* Returns: 0 on success, non-zero on failure
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*
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* This function sets the operating point of the APE.
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*/
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int prcmu_set_ape_opp(u8 opp)
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int db8500_prcmu_set_ape_opp(u8 opp)
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{
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int r = 0;
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@ -943,11 +943,11 @@ int prcmu_set_ape_opp(u8 opp)
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}
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/**
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* prcmu_get_ape_opp - get the current APE OPP
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* db8500_prcmu_get_ape_opp - get the current APE OPP
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*
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* Returns: the current APE OPP
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*/
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int prcmu_get_ape_opp(void)
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int db8500_prcmu_get_ape_opp(void)
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{
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return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
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}
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@ -1451,7 +1451,7 @@ int db8500_prcmu_config_esram0_deep_sleep(u8 state)
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return 0;
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}
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int prcmu_config_hotdog(u8 threshold)
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int db8500_prcmu_config_hotdog(u8 threshold)
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{
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mutex_lock(&mb4_transfer.lock);
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@ -1469,7 +1469,7 @@ int prcmu_config_hotdog(u8 threshold)
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return 0;
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}
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int prcmu_config_hotmon(u8 low, u8 high)
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int db8500_prcmu_config_hotmon(u8 low, u8 high)
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{
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mutex_lock(&mb4_transfer.lock);
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@ -1508,7 +1508,7 @@ static int config_hot_period(u16 val)
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return 0;
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}
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int prcmu_start_temp_sense(u16 cycles32k)
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int db8500_prcmu_start_temp_sense(u16 cycles32k)
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{
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if (cycles32k == 0xFFFF)
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return -EINVAL;
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@ -1516,7 +1516,7 @@ int prcmu_start_temp_sense(u16 cycles32k)
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return config_hot_period(cycles32k);
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}
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int prcmu_stop_temp_sense(void)
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int db8500_prcmu_stop_temp_sense(void)
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{
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return config_hot_period(0xFFFF);
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}
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@ -1545,7 +1545,7 @@ static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
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}
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int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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{
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BUG_ON(num == 0 || num > 0xf);
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return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
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@ -1553,17 +1553,17 @@ int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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A9WDOG_AUTO_OFF_DIS);
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}
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int prcmu_enable_a9wdog(u8 id)
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int db8500_prcmu_enable_a9wdog(u8 id)
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{
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return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
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}
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int prcmu_disable_a9wdog(u8 id)
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int db8500_prcmu_disable_a9wdog(u8 id)
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{
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return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
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}
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int prcmu_kick_a9wdog(u8 id)
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int db8500_prcmu_kick_a9wdog(u8 id)
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{
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return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
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}
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@ -1572,7 +1572,7 @@ int prcmu_kick_a9wdog(u8 id)
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* timeout is 28 bit, in ms.
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*/
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#define MAX_WATCHDOG_TIMEOUT 131000
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int prcmu_load_a9wdog(u8 id, u32 timeout)
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int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
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{
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if (timeout > MAX_WATCHDOG_TIMEOUT)
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/*
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@ -1825,9 +1825,9 @@ u16 db8500_prcmu_get_reset_code(void)
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}
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/**
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* prcmu_reset_modem - ask the PRCMU to reset modem
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* db8500_prcmu_reset_modem - ask the PRCMU to reset modem
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*/
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void prcmu_modem_reset(void)
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void db8500_prcmu_modem_reset(void)
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{
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mutex_lock(&mb1_transfer.lock);
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@ -2147,7 +2147,7 @@ void __init db8500_prcmu_early_init(void)
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}
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}
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static void __init db8500_prcmu_init_clkforce(void)
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static void __init init_prcm_registers(void)
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{
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u32 val;
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@ -2405,7 +2405,7 @@ static int __init db8500_prcmu_probe(struct platform_device *pdev)
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if (ux500_is_svp())
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return -ENODEV;
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db8500_prcmu_init_clkforce();
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init_prcm_registers();
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/* Clean up the mailbox interrupts after pre-kernel code. */
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writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
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@ -512,13 +512,9 @@ int prcmu_set_rc_a2p(enum romcode_write);
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enum romcode_read prcmu_get_rc_p2a(void);
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enum ap_pwrst prcmu_get_xp70_current_state(void);
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bool prcmu_has_arm_maxopp(void);
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int prcmu_set_ape_opp(u8 opp);
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int prcmu_get_ape_opp(void);
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struct prcmu_fw_version *prcmu_get_fw_version(void);
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int prcmu_request_ape_opp_100_voltage(bool enable);
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int prcmu_release_usb_wakeup_state(void);
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int prcmu_set_ddr_opp(u8 opp);
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int prcmu_get_ddr_opp(void);
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/* NOTE! Use regulator framework instead */
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int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
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void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
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@ -527,24 +523,24 @@ bool prcmu_is_auto_pm_enabled(void);
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int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
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int prcmu_set_clock_divider(u8 clock, u8 divider);
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int prcmu_config_hotdog(u8 threshold);
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int prcmu_config_hotmon(u8 low, u8 high);
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int prcmu_start_temp_sense(u16 cycles32k);
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int prcmu_stop_temp_sense(void);
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int db8500_prcmu_config_hotdog(u8 threshold);
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int db8500_prcmu_config_hotmon(u8 low, u8 high);
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int db8500_prcmu_start_temp_sense(u16 cycles32k);
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int db8500_prcmu_stop_temp_sense(void);
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int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
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void prcmu_ac_wake_req(void);
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void prcmu_ac_sleep_req(void);
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void prcmu_modem_reset(void);
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void db8500_prcmu_modem_reset(void);
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void prcmu_enable_spi2(void);
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void prcmu_disable_spi2(void);
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int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
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int prcmu_enable_a9wdog(u8 id);
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int prcmu_disable_a9wdog(u8 id);
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int prcmu_kick_a9wdog(u8 id);
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int prcmu_load_a9wdog(u8 id, u32 val);
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int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
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int db8500_prcmu_enable_a9wdog(u8 id);
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int db8500_prcmu_disable_a9wdog(u8 id);
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int db8500_prcmu_kick_a9wdog(u8 id);
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int db8500_prcmu_load_a9wdog(u8 id, u32 val);
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void db8500_prcmu_system_reset(u16 reset_code);
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int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
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@ -561,6 +557,10 @@ u16 db8500_prcmu_get_reset_code(void);
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bool db8500_prcmu_is_ac_wake_requested(void);
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int db8500_prcmu_set_arm_opp(u8 opp);
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int db8500_prcmu_get_arm_opp(void);
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int db8500_prcmu_set_ape_opp(u8 opp);
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int db8500_prcmu_get_ape_opp(void);
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int db8500_prcmu_set_ddr_opp(u8 opp);
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int db8500_prcmu_get_ddr_opp(void);
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#else /* !CONFIG_MFD_DB8500_PRCMU */
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@ -591,12 +591,12 @@ static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
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return NULL;
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}
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static inline int prcmu_set_ape_opp(u8 opp)
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static inline int db8500_prcmu_set_ape_opp(u8 opp)
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{
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return 0;
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}
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static inline int prcmu_get_ape_opp(void)
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static inline int db8500_prcmu_get_ape_opp(void)
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{
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return APE_100_OPP;
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}
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@ -611,12 +611,12 @@ static inline int prcmu_release_usb_wakeup_state(void)
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return 0;
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}
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static inline int prcmu_set_ddr_opp(u8 opp)
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static inline int db8500_prcmu_set_ddr_opp(u8 opp)
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{
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return 0;
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}
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static inline int prcmu_get_ddr_opp(void)
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static inline int db8500_prcmu_get_ddr_opp(void)
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{
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return DDR_100_OPP;
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}
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@ -625,7 +625,6 @@ static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
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{
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return 0;
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}
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static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
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struct prcmu_auto_pm_config *idle)
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{
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@ -646,22 +645,22 @@ static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
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return 0;
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}
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static inline int prcmu_config_hotdog(u8 threshold)
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static inline int db8500_prcmu_config_hotdog(u8 threshold)
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{
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return 0;
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}
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static inline int prcmu_config_hotmon(u8 low, u8 high)
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static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
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{
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return 0;
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}
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static inline int prcmu_start_temp_sense(u16 cycles32k)
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static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
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{
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return 0;
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}
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static inline int prcmu_stop_temp_sense(void)
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static inline int db8500_prcmu_stop_temp_sense(void)
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{
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return 0;
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}
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@ -680,7 +679,9 @@ static inline void prcmu_ac_wake_req(void) {}
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static inline void prcmu_ac_sleep_req(void) {}
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static inline void prcmu_modem_reset(void) {}
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static inline void db8500_prcmu_modem_reset(void) {}
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static inline void db8500_prcmu_system_reset(u16 reset_code) {}
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static inline int prcmu_enable_spi2(void)
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{
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@ -692,8 +693,6 @@ static inline int prcmu_disable_spi2(void)
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return 0;
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}
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static inline void db8500_prcmu_system_reset(u16 reset_code) {}
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static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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bool keep_ap_pll)
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{
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@ -741,27 +740,27 @@ static inline u16 db8500_prcmu_get_reset_code(void)
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return 0;
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}
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static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
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{
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return 0;
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}
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static inline int prcmu_enable_a9wdog(u8 id)
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static inline int db8500_prcmu_enable_a9wdog(u8 id)
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{
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return 0;
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}
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static inline int prcmu_disable_a9wdog(u8 id)
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static inline int db8500_prcmu_disable_a9wdog(u8 id)
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{
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return 0;
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}
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static inline int prcmu_kick_a9wdog(u8 id)
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static inline int db8500_prcmu_kick_a9wdog(u8 id)
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{
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return 0;
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}
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static inline int prcmu_load_a9wdog(u8 id, u32 val)
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static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
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{
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return 0;
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}
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@ -10,7 +10,7 @@
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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#include <asm/mach-types.h>
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#include <linux/err.h>
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/* PRCMU Wakeup defines */
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enum prcmu_wakeup_index {
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@ -218,9 +218,11 @@ enum ddr_pwrst {
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#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
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#include <mach/id.h>
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static inline void __init prcmu_early_init(void)
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{
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if (machine_is_u5500())
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if (cpu_is_u5500())
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return db5500_prcmu_early_init();
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else
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return db8500_prcmu_early_init();
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@ -229,7 +231,7 @@ static inline void __init prcmu_early_init(void)
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static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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bool keep_ap_pll)
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{
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if (machine_is_u5500())
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if (cpu_is_u5500())
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return db5500_prcmu_set_power_state(state, keep_ulp_clk,
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keep_ap_pll);
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else
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@ -239,7 +241,7 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
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static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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{
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if (machine_is_u5500())
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if (cpu_is_u5500())
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return -EINVAL;
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else
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return db8500_prcmu_set_epod(epod_id, epod_state);
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@ -247,7 +249,7 @@ static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
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static inline void prcmu_enable_wakeups(u32 wakeups)
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{
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if (machine_is_u5500())
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if (cpu_is_u5500())
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db5500_prcmu_enable_wakeups(wakeups);
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else
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db8500_prcmu_enable_wakeups(wakeups);
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@ -260,7 +262,7 @@ static inline void prcmu_disable_wakeups(void)
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static inline void prcmu_config_abb_event_readout(u32 abb_events)
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{
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if (machine_is_u5500())
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if (cpu_is_u5500())
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db5500_prcmu_config_abb_event_readout(abb_events);
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else
|
||||
db8500_prcmu_config_abb_event_readout(abb_events);
|
||||
|
|
@ -268,7 +270,7 @@ static inline void prcmu_config_abb_event_readout(u32 abb_events)
|
|||
|
||||
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
db5500_prcmu_get_abb_event_buffer(buf);
|
||||
else
|
||||
db8500_prcmu_get_abb_event_buffer(buf);
|
||||
|
|
@ -281,20 +283,34 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
|
|||
|
||||
static inline int prcmu_request_clock(u8 clock, bool enable)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_request_clock(clock, enable);
|
||||
else
|
||||
return db8500_prcmu_request_clock(clock, enable);
|
||||
}
|
||||
|
||||
int prcmu_set_ape_opp(u8 opp);
|
||||
int prcmu_get_ape_opp(void);
|
||||
int prcmu_set_ddr_opp(u8 opp);
|
||||
int prcmu_get_ddr_opp(void);
|
||||
unsigned long prcmu_clock_rate(u8 clock);
|
||||
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
|
||||
int prcmu_set_clock_rate(u8 clock, unsigned long rate);
|
||||
|
||||
static inline int prcmu_set_ddr_opp(u8 opp)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_set_ddr_opp(opp);
|
||||
}
|
||||
static inline int prcmu_get_ddr_opp(void)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_get_ddr_opp();
|
||||
}
|
||||
|
||||
static inline int prcmu_set_arm_opp(u8 opp)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_set_arm_opp(opp);
|
||||
|
|
@ -302,15 +318,31 @@ static inline int prcmu_set_arm_opp(u8 opp)
|
|||
|
||||
static inline int prcmu_get_arm_opp(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_get_arm_opp();
|
||||
}
|
||||
|
||||
static inline int prcmu_set_ape_opp(u8 opp)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_set_ape_opp(opp);
|
||||
}
|
||||
|
||||
static inline int prcmu_get_ape_opp(void)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_get_ape_opp();
|
||||
}
|
||||
|
||||
static inline void prcmu_system_reset(u16 reset_code)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_system_reset(reset_code);
|
||||
else
|
||||
return db8500_prcmu_system_reset(reset_code);
|
||||
|
|
@ -318,7 +350,7 @@ static inline void prcmu_system_reset(u16 reset_code)
|
|||
|
||||
static inline u16 prcmu_get_reset_code(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_get_reset_code();
|
||||
else
|
||||
return db8500_prcmu_get_reset_code();
|
||||
|
|
@ -326,10 +358,17 @@ static inline u16 prcmu_get_reset_code(void)
|
|||
|
||||
void prcmu_ac_wake_req(void);
|
||||
void prcmu_ac_sleep_req(void);
|
||||
void prcmu_modem_reset(void);
|
||||
static inline void prcmu_modem_reset(void)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return;
|
||||
else
|
||||
return db8500_prcmu_modem_reset();
|
||||
}
|
||||
|
||||
static inline bool prcmu_is_ac_wake_requested(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_is_ac_wake_requested();
|
||||
else
|
||||
return db8500_prcmu_is_ac_wake_requested();
|
||||
|
|
@ -337,7 +376,7 @@ static inline bool prcmu_is_ac_wake_requested(void)
|
|||
|
||||
static inline int prcmu_set_display_clocks(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_set_display_clocks();
|
||||
else
|
||||
return db8500_prcmu_set_display_clocks();
|
||||
|
|
@ -345,7 +384,7 @@ static inline int prcmu_set_display_clocks(void)
|
|||
|
||||
static inline int prcmu_disable_dsipll(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_disable_dsipll();
|
||||
else
|
||||
return db8500_prcmu_disable_dsipll();
|
||||
|
|
@ -353,7 +392,7 @@ static inline int prcmu_disable_dsipll(void)
|
|||
|
||||
static inline int prcmu_enable_dsipll(void)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return db5500_prcmu_enable_dsipll();
|
||||
else
|
||||
return db8500_prcmu_enable_dsipll();
|
||||
|
|
@ -361,11 +400,83 @@ static inline int prcmu_enable_dsipll(void)
|
|||
|
||||
static inline int prcmu_config_esram0_deep_sleep(u8 state)
|
||||
{
|
||||
if (machine_is_u5500())
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_config_esram0_deep_sleep(state);
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotdog(u8 threshold)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_config_hotdog(threshold);
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotmon(u8 low, u8 high)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_config_hotmon(low, high);
|
||||
}
|
||||
|
||||
static inline int prcmu_start_temp_sense(u16 cycles32k)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_start_temp_sense(cycles32k);
|
||||
}
|
||||
|
||||
static inline int prcmu_stop_temp_sense(void)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_stop_temp_sense();
|
||||
}
|
||||
|
||||
static inline int prcmu_enable_a9wdog(u8 id)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_enable_a9wdog(id);
|
||||
}
|
||||
|
||||
static inline int prcmu_disable_a9wdog(u8 id)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_disable_a9wdog(id);
|
||||
}
|
||||
|
||||
static inline int prcmu_kick_a9wdog(u8 id)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_kick_a9wdog(id);
|
||||
}
|
||||
|
||||
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_load_a9wdog(id, timeout);
|
||||
}
|
||||
|
||||
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
|
||||
{
|
||||
if (cpu_is_u5500())
|
||||
return -EINVAL;
|
||||
else
|
||||
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
|
||||
}
|
||||
#else
|
||||
|
||||
static inline void __init prcmu_early_init(void) {}
|
||||
|
|
@ -480,6 +591,26 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
|
|||
*buf = NULL;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotdog(u8 threshold)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_config_hotmon(u8 low, u8 high)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_start_temp_sense(u16 cycles32k)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int prcmu_stop_temp_sense(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* PRCMU QoS APE OPP class */
|
||||
|
|
|
|||
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