clk: tegra: pllc and pllxc should use pdiv_map
The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Peter De Schrijver
Mike Turquette
Родитель
081c9025f4
Коммит
053b525f6f
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@ -143,24 +143,6 @@
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#define divn_max(p) (divn_mask(p))
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#define divp_max(p) (1 << (divp_mask(p)))
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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/* PLLXC has 4-bit PDIV, but entry 15 is not allowed in h/w */
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#define PLLXC_PDIV_MAX 14
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/* non-monotonic mapping below is not a typo */
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static u8 pllxc_p[PLLXC_PDIV_MAX + 1] = {
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/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */
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/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32
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};
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#define PLLCX_PDIV_MAX 7
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static u8 pllcx_p[PLLCX_PDIV_MAX + 1] = {
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/* PDIV: 0, 1, 2, 3, 4, 5, 6, 7 */
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/* p: */ 1, 2, 3, 4, 6, 8, 12, 16
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};
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#endif
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static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
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{
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u32 val;
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@ -297,6 +279,39 @@ static void clk_pll_disable(struct clk_hw *hw)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
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if (p_tohw) {
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while (p_tohw->pdiv) {
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if (p_div <= p_tohw->pdiv)
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return p_tohw->hw_val;
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p_tohw++;
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}
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return -EINVAL;
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}
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return -EINVAL;
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}
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static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
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if (p_tohw) {
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while (p_tohw->pdiv) {
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if (p_div_hw == p_tohw->hw_val)
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return p_tohw->pdiv;
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p_tohw++;
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}
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return -EINVAL;
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}
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return 1 << p_div_hw;
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}
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static int _get_table_rate(struct clk_hw *hw,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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@ -326,9 +341,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
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unsigned long cfreq;
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u32 p_div = 0;
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int ret;
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switch (parent_rate) {
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case 12000000:
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@ -369,20 +384,16 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
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|| cfg->output_rate > pll->params->vco_max) {
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pr_err("%s: Failed to set %s rate %lu\n",
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__func__, __clk_get_name(hw->clk), rate);
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WARN_ON(1);
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return -EINVAL;
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}
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if (p_tohw) {
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p_div = 1 << p_div;
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while (p_tohw->pdiv) {
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if (p_div <= p_tohw->pdiv) {
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cfg->p = p_tohw->hw_val;
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break;
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}
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p_tohw++;
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}
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if (!p_tohw->pdiv)
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return -EINVAL;
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if (pll->params->pdiv_tohw) {
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ret = _p_div_to_hw(hw, 1 << p_div);
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if (ret < 0)
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return ret;
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else
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cfg->p = ret;
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} else
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cfg->p = p_div;
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@ -485,9 +496,10 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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}
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if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
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_calc_rate(hw, &cfg, rate, parent_rate))
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_calc_rate(hw, &cfg, rate, parent_rate)) {
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WARN_ON(1);
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return -EINVAL;
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}
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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@ -507,7 +519,6 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg;
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u64 output_rate = *prate;
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if (pll->flags & TEGRA_PLL_FIXED)
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return pll->fixed_rate;
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@ -517,13 +528,12 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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return __clk_get_rate(hw->clk);
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if (_get_table_rate(hw, &cfg, rate, *prate) &&
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_calc_rate(hw, &cfg, rate, *prate))
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_calc_rate(hw, &cfg, rate, *prate)) {
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WARN_ON(1);
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return -EINVAL;
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}
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output_rate *= cfg.n;
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do_div(output_rate, cfg.m * (1 << cfg.p));
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return output_rate;
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return cfg.output_rate;
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}
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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@ -531,7 +541,6 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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struct tegra_clk_pll_freq_table cfg;
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struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
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u32 val;
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u64 rate = parent_rate;
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int pdiv;
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@ -553,21 +562,11 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
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_get_pll_mnp(pll, &cfg);
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if (p_tohw) {
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while (p_tohw->pdiv) {
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if (cfg.p == p_tohw->hw_val) {
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pdiv = p_tohw->pdiv;
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break;
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}
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p_tohw++;
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}
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if (!p_tohw->pdiv) {
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WARN_ON(1);
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pdiv = 1;
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}
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} else
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pdiv = 1 << cfg.p;
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pdiv = _hw_to_p_div(hw, cfg.p);
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if (pdiv < 0) {
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WARN_ON(1);
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pdiv = 1;
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}
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cfg.m *= pdiv;
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@ -769,16 +768,22 @@ static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned int p;
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int p_div;
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if (!rate)
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return -EINVAL;
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p = DIV_ROUND_UP(pll->params->vco_min, rate);
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cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
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cfg->p = p;
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cfg->output_rate = rate * cfg->p;
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cfg->output_rate = rate * p;
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cfg->n = cfg->output_rate * cfg->m / parent_rate;
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p_div = _p_div_to_hw(hw, p);
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if (p_div < 0)
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return p_div;
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else
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cfg->p = p_div;
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if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
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return -EINVAL;
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@ -790,18 +795,25 @@ static int _pll_ramp_calc_pll(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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int err = 0;
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int err = 0, p_div;
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err = _get_table_rate(hw, cfg, rate, parent_rate);
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if (err < 0)
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err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
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else if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
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else {
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if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
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WARN_ON(1);
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err = -EINVAL;
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goto out;
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}
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p_div = _p_div_to_hw(hw, cfg->p);
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if (p_div < 0)
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return p_div;
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else
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cfg->p = p_div;
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}
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if (!cfg->p || (cfg->p > pll->params->max_p))
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if (cfg->p > pll->params->max_p)
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err = -EINVAL;
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out:
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@ -815,7 +827,6 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
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struct tegra_clk_pll_freq_table cfg, old_cfg;
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unsigned long flags = 0;
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int ret = 0;
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u8 old_p;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
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if (ret < 0)
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@ -826,11 +837,8 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
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_get_pll_mnp(pll, &old_cfg);
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old_p = pllxc_p[old_cfg.p];
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if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_p != cfg.p) {
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cfg.p -= 1;
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if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
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ret = _program_pll(hw, &cfg, rate);
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}
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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@ -842,15 +850,19 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_pll_freq_table cfg;
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int ret = 0;
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int ret = 0, p_div;
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u64 output_rate = *prate;
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ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
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if (ret < 0)
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return ret;
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p_div = _hw_to_p_div(hw, cfg.p);
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if (p_div < 0)
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return p_div;
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output_rate *= cfg.n;
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do_div(output_rate, cfg.m * cfg.p);
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do_div(output_rate, cfg.m * p_div);
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return output_rate;
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}
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@ -881,8 +893,6 @@ static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate,
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if (ret < 0)
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goto out;
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cfg.p -= 1;
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val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE);
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if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) {
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val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2);
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@ -1010,13 +1020,10 @@ static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
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static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_pll_freq_table cfg;
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struct tegra_clk_pll_freq_table cfg, old_cfg;
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struct tegra_clk_pll *pll = to_clk_pll(hw);
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unsigned long flags = 0;
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int state, ret = 0;
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u32 val;
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u16 old_m, old_n;
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u8 old_p;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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@ -1025,21 +1032,16 @@ static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
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if (ret < 0)
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goto out;
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val = pll_readl_base(pll);
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old_m = (val >> pll->divm_shift) & (divm_mask(pll));
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old_n = (val >> pll->divn_shift) & (divn_mask(pll));
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old_p = pllcx_p[(val >> pll->divp_shift) & (divp_mask(pll))];
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_get_pll_mnp(pll, &old_cfg);
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if (cfg.m != old_m) {
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if (cfg.m != old_cfg.m) {
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WARN_ON(1);
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goto out;
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}
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if (old_n == cfg.n && old_p == cfg.p)
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if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
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goto out;
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cfg.p -= 1;
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state = clk_pll_is_enabled(hw);
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if (state)
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_clk_pllc_disable(hw);
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