clk: ti: dpll: move omap3 DPLL functionality to clock driver
With the legacy clock support gone, OMAP3 generic DPLL code can now be moved over to the clock driver also. A few un-unused clkoutx2 functions are also removed at the same time. Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo
Родитель
192383d87b
Коммит
0565fb168d
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@ -189,15 +189,11 @@ obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o
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obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
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obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clock-common)
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# OMAP2 clock rate set data (old "OPP" data)
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obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
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@ -180,10 +180,6 @@ struct clksel {
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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void __init omap2_clk_disable_clkdm_control(void);
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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@ -29,82 +29,5 @@
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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/**
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* omap3_dpll4_set_rate - set rate for omap3 per-dpll
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* @hw: clock to change
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* @rate: target rate for clock
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* @parent_rate: rate of the parent clock
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*
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* Check if the current SoC supports the per-dpll reprogram operation
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* or not, and then do the rate change if supported. Returns -EINVAL
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* if not supported, 0 for success, and potential error codes from the
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* clock rate change.
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*/
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int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* According to the 12-5 CDP code from TI, "Limitation 2.5"
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* on 3430ES1 prevents us from changing DPLL multipliers or dividers
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* on DPLL4.
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*/
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if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
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pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
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}
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/**
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* omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
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* @hw: clock to change
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* @rate: target rate for clock
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* @parent_rate: rate of the parent clock
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* @index: parent index, 0 - reference clock, 1 - bypass clock
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*
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* Check if the current SoC support the per-dpll reprogram operation
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* or not, and then do the rate + parent change if supported. Returns
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* -EINVAL if not supported, 0 for success, and potential error codes
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* from the clock rate change.
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*/
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int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index)
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{
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if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
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pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
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index);
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}
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_prepare_enable(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_prepare_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable_unprepare(dpll5_m2_clk);
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clk_disable_unprepare(dpll5_clk);
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return;
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}
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@ -2,16 +2,18 @@ obj-y += clk.o autoidle.o clockdomain.o
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clk-common = dpll.o composite.o divider.o gate.o \
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fixed-factor.o mux.o apll.o \
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clkt_dpll.o clkt_iclk.o
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obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
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clk-3xxx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o dpll44xx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o dpll44xx.o
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clk-3xxx.o dpll3xxx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
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dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
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dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
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clk-dra7-atl.o dpll44xx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o
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clk-dra7-atl.o dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
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ifdef CONFIG_ATAGS
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obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
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@ -21,6 +21,13 @@
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#include "clock.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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static struct ti_dt_clk omap3xxx_clks[] = {
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DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
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DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
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@ -325,6 +332,30 @@ enum {
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OMAP3_SOC_OMAP3630,
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};
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/**
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* omap3_clk_lock_dpll5 - locks DPLL5
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*
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* Locks DPLL5 to a pre-defined frequency. This is required for proper
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* operation of USB.
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*/
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_prepare_enable(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_prepare_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable_unprepare(dpll5_m2_clk);
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clk_disable_unprepare(dpll5_clk);
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}
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static int __init omap3xxx_dt_clk_init(int soc_type)
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{
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if (soc_type == OMAP3_SOC_AM35XX || soc_type == OMAP3_SOC_OMAP3630 ||
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@ -173,11 +173,38 @@ void omap2_init_clk_hw_omap_clocks(struct clk *clk);
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int of_ti_clk_autoidle_setup(struct device_node *node);
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void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
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extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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extern const struct clk_hw_omap_ops clkhwops_iclk;
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extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
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u8 omap2_init_dpll_parent(struct clk_hw *hw);
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int omap3_noncore_dpll_enable(struct clk_hw *hw);
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void omap3_noncore_dpll_disable(struct clk_hw *hw);
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int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
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int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index);
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long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
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int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index);
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void omap3_clk_lock_dpll5(void);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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@ -27,8 +27,8 @@
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk/ti.h>
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#include "clockdomain.h"
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#include "clock.h"
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/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
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@ -37,6 +37,13 @@
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#define MAX_DPLL_WAIT_TRIES 1000000
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* Forward declarations */
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static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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/* Private functions */
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/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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@ -47,10 +54,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
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dd = clk->dpll_data;
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v = omap2_clk_readl(clk, dd->control_reg);
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v = ti_clk_ll_ops->clk_readl(dd->control_reg);
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v &= ~dd->enable_mask;
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v |= clken_bits << __ffs(dd->enable_mask);
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omap2_clk_writel(v, clk, dd->control_reg);
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ti_clk_ll_ops->clk_writel(v, dd->control_reg);
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}
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/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
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@ -66,14 +73,14 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
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state <<= __ffs(dd->idlest_mask);
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while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
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while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask)
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!= state) && i < MAX_DPLL_WAIT_TRIES) {
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i++;
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udelay(1);
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}
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if (i == MAX_DPLL_WAIT_TRIES) {
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printk(KERN_ERR "clock: %s failed transition to '%s'\n",
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pr_err("clock: %s failed transition to '%s'\n",
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clk_name, (state) ? "locked" : "bypassed");
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} else {
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pr_debug("clock: %s transition to '%s' in %d loops\n",
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@ -144,7 +151,8 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
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state <<= __ffs(dd->idlest_mask);
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/* Check if already locked */
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if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
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if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) ==
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state)
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goto done;
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ai = omap3_dpll_autoidle_read(clk);
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@ -308,14 +316,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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* only since freqsel field is no longer present on other devices.
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*/
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if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
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v = omap2_clk_readl(clk, dd->control_reg);
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v = ti_clk_ll_ops->clk_readl(dd->control_reg);
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v &= ~dd->freqsel_mask;
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v |= freqsel << __ffs(dd->freqsel_mask);
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omap2_clk_writel(v, clk, dd->control_reg);
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ti_clk_ll_ops->clk_writel(v, dd->control_reg);
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}
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/* Set DPLL multiplier, divider */
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v = omap2_clk_readl(clk, dd->mult_div1_reg);
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v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg);
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/* Handle Duty Cycle Correction */
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if (dd->dcc_mask) {
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@ -342,11 +350,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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v |= sd_div << __ffs(dd->sddiv_mask);
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}
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omap2_clk_writel(v, clk, dd->mult_div1_reg);
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ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg);
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/* Set 4X multiplier and low-power mode */
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if (dd->m4xen_mask || dd->lpmode_mask) {
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v = omap2_clk_readl(clk, dd->control_reg);
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v = ti_clk_ll_ops->clk_readl(dd->control_reg);
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if (dd->m4xen_mask) {
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if (dd->last_rounded_m4xen)
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@ -362,7 +370,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
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v &= ~dd->lpmode_mask;
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}
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omap2_clk_writel(v, clk, dd->control_reg);
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ti_clk_ll_ops->clk_writel(v, dd->control_reg);
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}
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/* We let the clock framework set the other output dividers later */
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@ -417,12 +425,12 @@ int omap3_noncore_dpll_enable(struct clk_hw *hw)
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return -EINVAL;
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if (clk->clkdm) {
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r = clkdm_clk_enable(clk->clkdm, hw->clk);
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r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
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if (r) {
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WARN(1,
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"%s: could not enable %s's clockdomain %s: %d\n",
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__func__, __clk_get_name(hw->clk),
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clk->clkdm->name, r);
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clk->clkdm_name, r);
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return r;
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}
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}
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@ -453,10 +461,9 @@ void omap3_noncore_dpll_disable(struct clk_hw *hw)
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_omap3_noncore_dpll_stop(clk);
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if (clk->clkdm)
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clkdm_clk_disable(clk->clkdm, hw->clk);
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ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
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}
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/* Non-CORE DPLL rate set code */
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/**
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@ -618,7 +625,7 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
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* -EINVAL if passed a null pointer or if the struct clk does not
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* appear to refer to a DPLL.
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*/
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
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static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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@ -631,7 +638,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
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if (!dd->autoidle_reg)
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return -EINVAL;
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||||
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
|
||||
v &= dd->autoidle_mask;
|
||||
v >>= __ffs(dd->autoidle_mask);
|
||||
|
||||
|
|
@ -647,7 +654,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
|
|||
* OMAP3430. The DPLL will enter low-power stop when its downstream
|
||||
* clocks are gated. No return value.
|
||||
*/
|
||||
void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
||||
static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
|
@ -665,11 +672,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
|||
* by writing 0x5 instead of 0x1. Add some mechanism to
|
||||
* optionally enter this mode.
|
||||
*/
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
|
||||
omap2_clk_writel(v, clk, dd->autoidle_reg);
|
||||
|
||||
ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -678,7 +684,7 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
|
|||
*
|
||||
* Disable DPLL automatic idle control. No return value.
|
||||
*/
|
||||
void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
|
||||
static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
|
|
@ -691,11 +697,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
|
|||
if (!dd->autoidle_reg)
|
||||
return;
|
||||
|
||||
v = omap2_clk_readl(clk, dd->autoidle_reg);
|
||||
v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg);
|
||||
v &= ~dd->autoidle_mask;
|
||||
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
|
||||
omap2_clk_writel(v, clk, dd->autoidle_reg);
|
||||
|
||||
ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg);
|
||||
}
|
||||
|
||||
/* Clock control for DPLL outputs */
|
||||
|
|
@ -753,7 +758,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
|||
|
||||
WARN_ON(!dd->enable_mask);
|
||||
|
||||
v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
|
||||
v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
|
||||
rate = parent_rate;
|
||||
|
|
@ -762,57 +767,59 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
|||
return rate;
|
||||
}
|
||||
|
||||
int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
const struct dpll_data *dd;
|
||||
u32 v;
|
||||
struct clk_hw_omap *pclk = NULL;
|
||||
|
||||
if (!*prate)
|
||||
return 0;
|
||||
|
||||
pclk = omap3_find_clkoutx2_dpll(hw);
|
||||
|
||||
if (!pclk)
|
||||
return 0;
|
||||
|
||||
dd = pclk->dpll_data;
|
||||
|
||||
/* TYPE J does not have a clkoutx2 */
|
||||
if (dd->flags & DPLL_J_TYPE) {
|
||||
*prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
|
||||
return *prate;
|
||||
}
|
||||
|
||||
WARN_ON(!dd->enable_mask);
|
||||
|
||||
v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
|
||||
v >>= __ffs(dd->enable_mask);
|
||||
|
||||
/* If in bypass, the rate is fixed to the bypass rate*/
|
||||
if (v != OMAP3XXX_EN_DPLL_LOCKED)
|
||||
return *prate;
|
||||
|
||||
if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
|
||||
unsigned long best_parent;
|
||||
|
||||
best_parent = (rate / 2);
|
||||
*prate = __clk_round_rate(__clk_get_parent(hw->clk),
|
||||
best_parent);
|
||||
}
|
||||
|
||||
return *prate * 2;
|
||||
}
|
||||
|
||||
/* OMAP3/4 non-CORE DPLL clkops */
|
||||
const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
|
||||
.allow_idle = omap3_dpll_allow_idle,
|
||||
.deny_idle = omap3_dpll_deny_idle,
|
||||
};
|
||||
|
||||
/**
|
||||
* omap3_dpll4_set_rate - set rate for omap3 per-dpll
|
||||
* @hw: clock to change
|
||||
* @rate: target rate for clock
|
||||
* @parent_rate: rate of the parent clock
|
||||
*
|
||||
* Check if the current SoC supports the per-dpll reprogram operation
|
||||
* or not, and then do the rate change if supported. Returns -EINVAL
|
||||
* if not supported, 0 for success, and potential error codes from the
|
||||
* clock rate change.
|
||||
*/
|
||||
int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
/*
|
||||
* According to the 12-5 CDP code from TI, "Limitation 2.5"
|
||||
* on 3430ES1 prevents us from changing DPLL multipliers or dividers
|
||||
* on DPLL4.
|
||||
*/
|
||||
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
|
||||
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
|
||||
}
|
||||
|
||||
/**
|
||||
* omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
|
||||
* @hw: clock to change
|
||||
* @rate: target rate for clock
|
||||
* @parent_rate: rate of the parent clock
|
||||
* @index: parent index, 0 - reference clock, 1 - bypass clock
|
||||
*
|
||||
* Check if the current SoC support the per-dpll reprogram operation
|
||||
* or not, and then do the rate + parent change if supported. Returns
|
||||
* -EINVAL if not supported, 0 for success, and potential error codes
|
||||
* from the clock rate change.
|
||||
*/
|
||||
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate, u8 index)
|
||||
{
|
||||
if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
|
||||
pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
|
||||
index);
|
||||
}
|
||||
|
|
@ -271,41 +271,13 @@ extern const struct clk_ops ti_clk_mux_ops;
|
|||
|
||||
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
|
||||
|
||||
int omap3_noncore_dpll_enable(struct clk_hw *hw);
|
||||
void omap3_noncore_dpll_disable(struct clk_hw *hw);
|
||||
int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
|
||||
int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate,
|
||||
u8 index);
|
||||
long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long min_rate,
|
||||
unsigned long max_rate,
|
||||
unsigned long *best_parent_rate,
|
||||
struct clk_hw **best_parent_clk);
|
||||
unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
|
||||
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
|
||||
unsigned long *parent_rate);
|
||||
void omap2_init_clk_clkdm(struct clk_hw *clk);
|
||||
unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate);
|
||||
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
|
||||
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
|
||||
int omap2_clk_disable_autoidle_all(void);
|
||||
int omap2_clk_enable_autoidle_all(void);
|
||||
int omap2_clk_allow_idle(struct clk *clk);
|
||||
int omap2_clk_deny_idle(struct clk *clk);
|
||||
int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate, u8 index);
|
||||
int omap2_dflt_clk_enable(struct clk_hw *hw);
|
||||
void omap2_dflt_clk_disable(struct clk_hw *hw);
|
||||
int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
|
||||
|
|
@ -317,7 +289,6 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
|
|||
void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
|
||||
void __iomem **idlest_reg,
|
||||
u8 *idlest_bit, u8 *idlest_val);
|
||||
void omap3_clk_lock_dpll5(void);
|
||||
unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
|
||||
unsigned long parent_rate);
|
||||
int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
|
||||
|
|
@ -365,7 +336,6 @@ const struct ti_clk_features *ti_clk_get_features(void);
|
|||
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
|
||||
extern const struct clk_hw_omap_ops clkhwops_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
|
||||
extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
|
||||
|
|
|
|||
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