A couple of GVT fixes, and a GGTT mmapping fix.
-----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEFWWmW3ewYy4RJOWc05gHnSar7m8FAls+DhEACgkQ05gHnSar 7m/QRA/8CmWdYgRLWT9gc2OB8uWVWsKyMeO5Uvoy/3lnWPlmFO4J6wvOptVSxlfh yR89jIoxdb4204P5vjuI3dHD5WQFCiQzDTP438oIhFxc6KXr2osDMoy1laIpG31v XrV7dXk3lGOdkP+l6es0L4xo2IHpR9NLNtb61HNHmJFbsAPONG55wUW0VNDx17DY DyhyZtnI8Y+WZ8it95dn1E11MgKrQIpHKeWqAhJor2XaS6vHJkfzJFuNQh2V1dKm n9IbE1YexaYxC6ky7CEbDuSBu23NVsqZ0+QUHoq2qGj7s2i5PBzahCPZ+9TltypF fTCjtpXEhO3E2LCSUm/JEmZbl8zgKEzDBSRW/XMU2ryQby+AVTvtHIaFn9G1B8Ax dv0QCisNWmvA9m+jq2NfblffoD5aY0ME1eb6wKYf5XDIq8uysXHgSXP/3riaNcBb z4j/Bvf+qaBwxuOrbeZvwsjR8sgBxZR8sazUtUF1baiUODbya4dmWSiuQrBrDPtS 5ZPw/glQhKcyFhAIN014Tn4opgbWnlMOgRaJOqb5EQ4tEcr6sCsiQBqgOE+A5eMR TWl27CsKkBvAthgemvLudlEdYkOe2OKwmUCuHhdYQAFL/nV4QzfP+7hpo17M8BIt hMYqmxf9pfHXILUkgDgv98q95ZaDkic5Aaa9nUQZVJ7iUQGpeZ0= =Euzf -----END PGP SIGNATURE----- Merge tag 'drm-intel-fixes-2018-07-05' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes A couple of GVT fixes, and a GGTT mmapping fix. Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/8736wxq35t.fsf@intel.com
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Коммит
0581a5cb06
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@ -196,7 +196,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
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TRANS_DDI_PORT_MASK);
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vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
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(PORT_B << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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@ -216,7 +216,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
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TRANS_DDI_PORT_MASK);
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vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
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(PORT_C << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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@ -236,7 +236,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
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TRANS_DDI_PORT_MASK);
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vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
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(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
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(PORT_D << TRANS_DDI_PORT_SHIFT) |
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TRANS_DDI_FUNC_ENABLE);
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if (IS_BROADWELL(dev_priv)) {
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@ -1592,6 +1592,7 @@ static struct intel_vgpu_mm *intel_vgpu_create_ggtt_mm(struct intel_vgpu *vgpu)
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vgpu_free_mm(mm);
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return ERR_PTR(-ENOMEM);
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}
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mm->ggtt_mm.last_partial_off = -1UL;
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return mm;
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}
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@ -1616,6 +1617,7 @@ void _intel_vgpu_mm_release(struct kref *mm_ref)
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invalidate_ppgtt_mm(mm);
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} else {
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vfree(mm->ggtt_mm.virtual_ggtt);
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mm->ggtt_mm.last_partial_off = -1UL;
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}
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vgpu_free_mm(mm);
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@ -1868,6 +1870,62 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
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memcpy((void *)&e.val64 + (off & (info->gtt_entry_size - 1)), p_data,
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bytes);
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/* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
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* write, we assume the two 4 bytes writes are consecutive.
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* Otherwise, we abort and report error
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*/
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if (bytes < info->gtt_entry_size) {
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if (ggtt_mm->ggtt_mm.last_partial_off == -1UL) {
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/* the first partial part*/
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ggtt_mm->ggtt_mm.last_partial_off = off;
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ggtt_mm->ggtt_mm.last_partial_data = e.val64;
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return 0;
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} else if ((g_gtt_index ==
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(ggtt_mm->ggtt_mm.last_partial_off >>
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info->gtt_entry_size_shift)) &&
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(off != ggtt_mm->ggtt_mm.last_partial_off)) {
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/* the second partial part */
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int last_off = ggtt_mm->ggtt_mm.last_partial_off &
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(info->gtt_entry_size - 1);
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memcpy((void *)&e.val64 + last_off,
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(void *)&ggtt_mm->ggtt_mm.last_partial_data +
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last_off, bytes);
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ggtt_mm->ggtt_mm.last_partial_off = -1UL;
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} else {
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int last_offset;
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gvt_vgpu_err("failed to populate guest ggtt entry: abnormal ggtt entry write sequence, last_partial_off=%lx, offset=%x, bytes=%d, ggtt entry size=%d\n",
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ggtt_mm->ggtt_mm.last_partial_off, off,
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bytes, info->gtt_entry_size);
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/* set host ggtt entry to scratch page and clear
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* virtual ggtt entry as not present for last
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* partially write offset
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*/
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last_offset = ggtt_mm->ggtt_mm.last_partial_off &
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(~(info->gtt_entry_size - 1));
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ggtt_get_host_entry(ggtt_mm, &m, last_offset);
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ggtt_invalidate_pte(vgpu, &m);
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ops->set_pfn(&m, gvt->gtt.scratch_mfn);
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ops->clear_present(&m);
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ggtt_set_host_entry(ggtt_mm, &m, last_offset);
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ggtt_invalidate(gvt->dev_priv);
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ggtt_get_guest_entry(ggtt_mm, &e, last_offset);
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ops->clear_present(&e);
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ggtt_set_guest_entry(ggtt_mm, &e, last_offset);
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ggtt_mm->ggtt_mm.last_partial_off = off;
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ggtt_mm->ggtt_mm.last_partial_data = e.val64;
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return 0;
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}
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}
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if (ops->test_present(&e)) {
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gfn = ops->get_pfn(&e);
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m = e;
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@ -150,6 +150,8 @@ struct intel_vgpu_mm {
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} ppgtt_mm;
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struct {
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void *virtual_ggtt;
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unsigned long last_partial_off;
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u64 last_partial_data;
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} ggtt_mm;
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};
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};
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@ -2002,7 +2002,6 @@ int i915_gem_fault(struct vm_fault *vmf)
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bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
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struct i915_vma *vma;
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pgoff_t page_offset;
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unsigned int flags;
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int ret;
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/* We don't use vmf->pgoff since that has the fake offset */
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@ -2038,27 +2037,34 @@ int i915_gem_fault(struct vm_fault *vmf)
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goto err_unlock;
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}
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/* If the object is smaller than a couple of partial vma, it is
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* not worth only creating a single partial vma - we may as well
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* clear enough space for the full object.
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*/
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flags = PIN_MAPPABLE;
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if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT)
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flags |= PIN_NONBLOCK | PIN_NONFAULT;
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/* Now pin it into the GTT as needed */
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags);
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
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PIN_MAPPABLE |
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PIN_NONBLOCK |
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PIN_NONFAULT);
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if (IS_ERR(vma)) {
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/* Use a partial view if it is bigger than available space */
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struct i915_ggtt_view view =
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compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES);
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unsigned int flags;
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/* Userspace is now writing through an untracked VMA, abandon
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flags = PIN_MAPPABLE;
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if (view.type == I915_GGTT_VIEW_NORMAL)
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flags |= PIN_NONBLOCK; /* avoid warnings for pinned */
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/*
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* Userspace is now writing through an untracked VMA, abandon
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* all hope that the hardware is able to track future writes.
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*/
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obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
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if (IS_ERR(vma) && !view.type) {
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flags = PIN_MAPPABLE;
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view.type = I915_GGTT_VIEW_PARTIAL;
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags);
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}
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}
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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@ -109,7 +109,7 @@ vma_create(struct drm_i915_gem_object *obj,
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obj->base.size >> PAGE_SHIFT));
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vma->size = view->partial.size;
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vma->size <<= PAGE_SHIFT;
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GEM_BUG_ON(vma->size >= obj->base.size);
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GEM_BUG_ON(vma->size > obj->base.size);
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} else if (view->type == I915_GGTT_VIEW_ROTATED) {
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vma->size = intel_rotation_info_size(&view->rotated);
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vma->size <<= PAGE_SHIFT;
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