x86: code cleanups in arch/x86/kernel/pci-gart_64.c
code cleanups:
errors lines of code errors/KLOC
arch/x86/kernel/pci-gart_64.c 183 748 244.6
arch/x86/kernel/pci-gart_64.c 0 790 0
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Ingo Molnar
Родитель
e8d591dc71
Коммит
05fccb0e38
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@ -1,12 +1,12 @@
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/*
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* Dynamic DMA mapping support for AMD Hammer.
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*
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*
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* Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
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* This allows to use PCI devices that only support 32bit addresses on systems
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* with more than 4GB.
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* with more than 4GB.
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*
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* See Documentation/DMA-mapping.txt for the interface specification.
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*
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*
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* Copyright 2002 Andi Kleen, SuSE Labs.
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* Subject to the GNU General Public License v2 only.
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*/
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@ -37,23 +37,26 @@
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#include <asm/k8.h>
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static unsigned long iommu_bus_base; /* GART remapping area (physical) */
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static unsigned long iommu_size; /* size of remapping area bytes */
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static unsigned long iommu_size; /* size of remapping area bytes */
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static unsigned long iommu_pages; /* .. and in pages */
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static u32 *iommu_gatt_base; /* Remapping table */
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static u32 *iommu_gatt_base; /* Remapping table */
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/* If this is disabled the IOMMU will use an optimized flushing strategy
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of only flushing when an mapping is reused. With it true the GART is flushed
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for every mapping. Problem is that doing the lazy flush seems to trigger
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bugs with some popular PCI cards, in particular 3ware (but has been also
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also seen with Qlogic at least). */
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/*
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* If this is disabled the IOMMU will use an optimized flushing strategy
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* of only flushing when an mapping is reused. With it true the GART is
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* flushed for every mapping. Problem is that doing the lazy flush seems
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* to trigger bugs with some popular PCI cards, in particular 3ware (but
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* has been also also seen with Qlogic at least).
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*/
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int iommu_fullflush = 1;
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/* Allocation bitmap for the remapping area */
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/* Allocation bitmap for the remapping area: */
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static DEFINE_SPINLOCK(iommu_bitmap_lock);
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static unsigned long *iommu_gart_bitmap; /* guarded by iommu_bitmap_lock */
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/* Guarded by iommu_bitmap_lock: */
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static unsigned long *iommu_gart_bitmap;
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static u32 gart_unmapped_entry;
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static u32 gart_unmapped_entry;
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#define GPTE_VALID 1
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#define GPTE_COHERENT 2
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@ -61,10 +64,10 @@ static u32 gart_unmapped_entry;
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(((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
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#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
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#define to_pages(addr,size) \
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#define to_pages(addr, size) \
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(round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
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#define EMERGENCY_PAGES 32 /* = 128KB */
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#define EMERGENCY_PAGES 32 /* = 128KB */
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#ifdef CONFIG_AGP
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#define AGPEXTERN extern
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@ -77,130 +80,152 @@ AGPEXTERN int agp_memory_reserved;
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AGPEXTERN __u32 *agp_gatt_table;
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static unsigned long next_bit; /* protected by iommu_bitmap_lock */
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static int need_flush; /* global flush state. set for each gart wrap */
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static int need_flush; /* global flush state. set for each gart wrap */
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static unsigned long alloc_iommu(int size)
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{
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static unsigned long alloc_iommu(int size)
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{
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unsigned long offset, flags;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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offset = find_next_zero_string(iommu_gart_bitmap,next_bit,iommu_pages,size);
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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offset = find_next_zero_string(iommu_gart_bitmap, next_bit,
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iommu_pages, size);
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if (offset == -1) {
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need_flush = 1;
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offset = find_next_zero_string(iommu_gart_bitmap,0,iommu_pages,size);
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offset = find_next_zero_string(iommu_gart_bitmap, 0,
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iommu_pages, size);
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}
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if (offset != -1) {
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set_bit_string(iommu_gart_bitmap, offset, size);
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next_bit = offset+size;
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if (next_bit >= iommu_pages) {
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if (offset != -1) {
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set_bit_string(iommu_gart_bitmap, offset, size);
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next_bit = offset+size;
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if (next_bit >= iommu_pages) {
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next_bit = 0;
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need_flush = 1;
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}
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}
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}
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}
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if (iommu_fullflush)
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need_flush = 1;
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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return offset;
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}
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}
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static void free_iommu(unsigned long offset, int size)
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{
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{
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unsigned long flags;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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__clear_bit_string(iommu_gart_bitmap, offset, size);
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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}
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}
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/*
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/*
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* Use global flush state to avoid races with multiple flushers.
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*/
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static void flush_gart(void)
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{
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{
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unsigned long flags;
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spin_lock_irqsave(&iommu_bitmap_lock, flags);
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if (need_flush) {
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k8_flush_garts();
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need_flush = 0;
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}
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}
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spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
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}
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}
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#ifdef CONFIG_IOMMU_LEAK
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#define SET_LEAK(x) if (iommu_leak_tab) \
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iommu_leak_tab[x] = __builtin_return_address(0);
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#define CLEAR_LEAK(x) if (iommu_leak_tab) \
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iommu_leak_tab[x] = NULL;
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#define SET_LEAK(x) \
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do { \
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if (iommu_leak_tab) \
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iommu_leak_tab[x] = __builtin_return_address(0);\
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} while (0)
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#define CLEAR_LEAK(x) \
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do { \
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if (iommu_leak_tab) \
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iommu_leak_tab[x] = NULL; \
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} while (0)
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/* Debugging aid for drivers that don't free their IOMMU tables */
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static void **iommu_leak_tab;
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static void **iommu_leak_tab;
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static int leak_trace;
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static int iommu_leak_pages = 20;
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static void dump_leak(void)
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{
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int i;
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static int dump;
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if (dump || !iommu_leak_tab) return;
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static int dump;
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if (dump || !iommu_leak_tab)
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return;
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dump = 1;
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show_stack(NULL,NULL);
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/* Very crude. dump some from the end of the table too */
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printk("Dumping %d pages from end of IOMMU:\n", iommu_leak_pages);
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for (i = 0; i < iommu_leak_pages; i+=2) {
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printk("%lu: ", iommu_pages-i);
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show_stack(NULL, NULL);
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/* Very crude. dump some from the end of the table too */
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printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
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iommu_leak_pages);
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for (i = 0; i < iommu_leak_pages; i += 2) {
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printk(KERN_DEBUG "%lu: ", iommu_pages-i);
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printk_address((unsigned long) iommu_leak_tab[iommu_pages-i]);
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printk("%c", (i+1)%2 == 0 ? '\n' : ' ');
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}
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printk("\n");
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printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
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}
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printk(KERN_DEBUG "\n");
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}
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#else
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#define SET_LEAK(x)
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#define CLEAR_LEAK(x)
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# define SET_LEAK(x)
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# define CLEAR_LEAK(x)
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#endif
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static void iommu_full(struct device *dev, size_t size, int dir)
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{
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/*
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/*
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* Ran out of IOMMU space for this operation. This is very bad.
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* Unfortunately the drivers cannot handle this operation properly.
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* Return some non mapped prereserved space in the aperture and
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* Return some non mapped prereserved space in the aperture and
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* let the Northbridge deal with it. This will result in garbage
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* in the IO operation. When the size exceeds the prereserved space
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* memory corruption will occur or random memory will be DMAed
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* memory corruption will occur or random memory will be DMAed
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* out. Hopefully no network devices use single mappings that big.
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*/
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printk(KERN_ERR
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"PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n",
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size, dev->bus_id);
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*/
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printk(KERN_ERR
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"PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n",
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size, dev->bus_id);
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if (size > PAGE_SIZE*EMERGENCY_PAGES) {
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if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
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panic("PCI-DMA: Memory would be corrupted\n");
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if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
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panic(KERN_ERR "PCI-DMA: Random memory would be DMAed\n");
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}
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if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
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panic(KERN_ERR
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"PCI-DMA: Random memory would be DMAed\n");
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}
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#ifdef CONFIG_IOMMU_LEAK
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dump_leak();
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dump_leak();
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#endif
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}
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static inline int need_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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u64 mask = *dev->dma_mask;
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int high = addr + size > mask;
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int mmu = high;
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if (force_iommu)
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mmu = 1;
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return mmu;
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}
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static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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static inline int
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need_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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u64 mask = *dev->dma_mask;
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int high = addr + size > mask;
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int mmu = high;
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return mmu;
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if (force_iommu)
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mmu = 1;
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return mmu;
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}
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static inline int
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nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
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{
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u64 mask = *dev->dma_mask;
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int high = addr + size > mask;
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int mmu = high;
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return mmu;
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}
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/* Map a single continuous physical area into the IOMMU.
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@ -208,13 +233,14 @@ static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t
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*/
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static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
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size_t size, int dir)
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{
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{
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unsigned long npages = to_pages(phys_mem, size);
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unsigned long iommu_page = alloc_iommu(npages);
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int i;
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if (iommu_page == -1) {
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if (!nonforced_iommu(dev, phys_mem, size))
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return phys_mem;
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return phys_mem;
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if (panic_on_overflow)
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panic("dma_map_area overflow %lu bytes\n", size);
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iommu_full(dev, size, dir);
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@ -229,35 +255,39 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
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return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
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}
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static dma_addr_t gart_map_simple(struct device *dev, char *buf,
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size_t size, int dir)
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static dma_addr_t
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gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
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{
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dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
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flush_gart();
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return map;
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}
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/* Map a single area into the IOMMU */
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static dma_addr_t gart_map_single(struct device *dev, void *addr, size_t size, int dir)
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static dma_addr_t
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gart_map_single(struct device *dev, void *addr, size_t size, int dir)
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{
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unsigned long phys_mem, bus;
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if (!dev)
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dev = &fallback_dev;
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phys_mem = virt_to_phys(addr);
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phys_mem = virt_to_phys(addr);
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if (!need_iommu(dev, phys_mem, size))
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return phys_mem;
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return phys_mem;
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bus = gart_map_simple(dev, addr, size, dir);
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return bus;
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return bus;
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}
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/*
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* Free a DMA mapping.
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*/
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static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
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size_t size, int direction)
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size_t size, int direction)
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{
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unsigned long iommu_page;
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int npages;
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@ -266,6 +296,7 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
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if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
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dma_addr >= iommu_bus_base + iommu_size)
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return;
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iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
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npages = to_pages(dma_addr, size);
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for (i = 0; i < npages; i++) {
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@ -278,7 +309,8 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
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/*
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* Wrapper for pci_unmap_single working with scatterlists.
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*/
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static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
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static void
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gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
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{
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struct scatterlist *s;
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int i;
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@ -303,12 +335,13 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
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for_each_sg(sg, s, nents, i) {
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unsigned long addr = sg_phys(s);
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if (nonforced_iommu(dev, addr, s->length)) {
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if (nonforced_iommu(dev, addr, s->length)) {
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addr = dma_map_area(dev, addr, s->length, dir);
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if (addr == bad_dma_address) {
|
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if (i > 0)
|
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if (addr == bad_dma_address) {
|
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if (i > 0)
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gart_unmap_sg(dev, sg, i, dir);
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nents = 0;
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nents = 0;
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sg[0].dma_length = 0;
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break;
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}
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@ -317,15 +350,16 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
|
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s->dma_length = s->length;
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}
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flush_gart();
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|
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return nents;
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}
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|
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/* Map multiple scatterlist entries continuous into the first. */
|
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static int __dma_map_cont(struct scatterlist *start, int nelems,
|
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struct scatterlist *sout, unsigned long pages)
|
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struct scatterlist *sout, unsigned long pages)
|
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{
|
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unsigned long iommu_start = alloc_iommu(pages);
|
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unsigned long iommu_page = iommu_start;
|
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unsigned long iommu_page = iommu_start;
|
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struct scatterlist *s;
|
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int i;
|
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|
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|
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@ -335,32 +369,33 @@ static int __dma_map_cont(struct scatterlist *start, int nelems,
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for_each_sg(start, s, nelems, i) {
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unsigned long pages, addr;
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unsigned long phys_addr = s->dma_address;
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|
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BUG_ON(s != start && s->offset);
|
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if (s == start) {
|
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sout->dma_address = iommu_bus_base;
|
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sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
|
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sout->dma_length = s->length;
|
||||
} else {
|
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sout->dma_length += s->length;
|
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} else {
|
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sout->dma_length += s->length;
|
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}
|
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|
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addr = phys_addr;
|
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pages = to_pages(s->offset, s->length);
|
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while (pages--) {
|
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iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
|
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pages = to_pages(s->offset, s->length);
|
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while (pages--) {
|
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iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
|
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SET_LEAK(iommu_page);
|
||||
addr += PAGE_SIZE;
|
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iommu_page++;
|
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}
|
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}
|
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BUG_ON(iommu_page - iommu_start != pages);
|
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}
|
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BUG_ON(iommu_page - iommu_start != pages);
|
||||
|
||||
return 0;
|
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}
|
||||
|
||||
static inline int dma_map_cont(struct scatterlist *start, int nelems,
|
||||
struct scatterlist *sout,
|
||||
unsigned long pages, int need)
|
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static inline int
|
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dma_map_cont(struct scatterlist *start, int nelems, struct scatterlist *sout,
|
||||
unsigned long pages, int need)
|
||||
{
|
||||
if (!need) {
|
||||
BUG_ON(nelems != 1);
|
||||
|
|
@ -370,22 +405,19 @@ static inline int dma_map_cont(struct scatterlist *start, int nelems,
|
|||
}
|
||||
return __dma_map_cont(start, nelems, sout, pages);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* DMA map all entries in a scatterlist.
|
||||
* Merge chunks that have page aligned sizes into a continuous mapping.
|
||||
* Merge chunks that have page aligned sizes into a continuous mapping.
|
||||
*/
|
||||
static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
||||
int dir)
|
||||
static int
|
||||
gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
|
||||
{
|
||||
int i;
|
||||
int out;
|
||||
int start;
|
||||
unsigned long pages = 0;
|
||||
int need = 0, nextneed;
|
||||
struct scatterlist *s, *ps, *start_sg, *sgmap;
|
||||
int need = 0, nextneed, i, out, start;
|
||||
unsigned long pages = 0;
|
||||
|
||||
if (nents == 0)
|
||||
if (nents == 0)
|
||||
return 0;
|
||||
|
||||
if (!dev)
|
||||
|
|
@ -397,15 +429,19 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|||
ps = NULL; /* shut up gcc */
|
||||
for_each_sg(sg, s, nents, i) {
|
||||
dma_addr_t addr = sg_phys(s);
|
||||
s->dma_address = addr;
|
||||
BUG_ON(s->length == 0);
|
||||
|
||||
nextneed = need_iommu(dev, addr, s->length);
|
||||
s->dma_address = addr;
|
||||
BUG_ON(s->length == 0);
|
||||
|
||||
nextneed = need_iommu(dev, addr, s->length);
|
||||
|
||||
/* Handle the previous not yet processed entries */
|
||||
if (i > start) {
|
||||
/* Can only merge when the last chunk ends on a page
|
||||
boundary and the new one doesn't have an offset. */
|
||||
/*
|
||||
* Can only merge when the last chunk ends on a
|
||||
* page boundary and the new one doesn't have an
|
||||
* offset.
|
||||
*/
|
||||
if (!iommu_merge || !nextneed || !need || s->offset ||
|
||||
(ps->offset + ps->length) % PAGE_SIZE) {
|
||||
if (dma_map_cont(start_sg, i - start, sgmap,
|
||||
|
|
@ -436,6 +472,7 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|||
error:
|
||||
flush_gart();
|
||||
gart_unmap_sg(dev, sg, out, dir);
|
||||
|
||||
/* When it was forced or merged try again in a dumb way */
|
||||
if (force_iommu || iommu_merge) {
|
||||
out = dma_map_sg_nonforce(dev, sg, nents, dir);
|
||||
|
|
@ -444,64 +481,68 @@ error:
|
|||
}
|
||||
if (panic_on_overflow)
|
||||
panic("dma_map_sg: overflow on %lu pages\n", pages);
|
||||
|
||||
iommu_full(dev, pages << PAGE_SHIFT, dir);
|
||||
for_each_sg(sg, s, nents, i)
|
||||
s->dma_address = bad_dma_address;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int no_agp;
|
||||
|
||||
static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
|
||||
{
|
||||
unsigned long a;
|
||||
if (!iommu_size) {
|
||||
iommu_size = aper_size;
|
||||
if (!no_agp)
|
||||
iommu_size /= 2;
|
||||
}
|
||||
{
|
||||
unsigned long a;
|
||||
|
||||
a = aper + iommu_size;
|
||||
if (!iommu_size) {
|
||||
iommu_size = aper_size;
|
||||
if (!no_agp)
|
||||
iommu_size /= 2;
|
||||
}
|
||||
|
||||
a = aper + iommu_size;
|
||||
iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a;
|
||||
|
||||
if (iommu_size < 64*1024*1024)
|
||||
if (iommu_size < 64*1024*1024) {
|
||||
printk(KERN_WARNING
|
||||
"PCI-DMA: Warning: Small IOMMU %luMB. Consider increasing the AGP aperture in BIOS\n",iommu_size>>20);
|
||||
|
||||
"PCI-DMA: Warning: Small IOMMU %luMB."
|
||||
" Consider increasing the AGP aperture in BIOS\n",
|
||||
iommu_size >> 20);
|
||||
}
|
||||
|
||||
return iommu_size;
|
||||
}
|
||||
}
|
||||
|
||||
static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
|
||||
{
|
||||
unsigned aper_size = 0, aper_base_32;
|
||||
static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
|
||||
{
|
||||
unsigned aper_size = 0, aper_base_32, aper_order;
|
||||
u64 aper_base;
|
||||
unsigned aper_order;
|
||||
|
||||
pci_read_config_dword(dev, 0x94, &aper_base_32);
|
||||
pci_read_config_dword(dev, 0x94, &aper_base_32);
|
||||
pci_read_config_dword(dev, 0x90, &aper_order);
|
||||
aper_order = (aper_order >> 1) & 7;
|
||||
aper_order = (aper_order >> 1) & 7;
|
||||
|
||||
aper_base = aper_base_32 & 0x7fff;
|
||||
aper_base = aper_base_32 & 0x7fff;
|
||||
aper_base <<= 25;
|
||||
|
||||
aper_size = (32 * 1024 * 1024) << aper_order;
|
||||
if (aper_base + aper_size > 0x100000000UL || !aper_size)
|
||||
aper_size = (32 * 1024 * 1024) << aper_order;
|
||||
if (aper_base + aper_size > 0x100000000UL || !aper_size)
|
||||
aper_base = 0;
|
||||
|
||||
*size = aper_size;
|
||||
return aper_base;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* Private Northbridge GATT initialization in case we cannot use the
|
||||
* AGP driver for some reason.
|
||||
* AGP driver for some reason.
|
||||
*/
|
||||
static __init int init_k8_gatt(struct agp_kern_info *info)
|
||||
{
|
||||
{
|
||||
unsigned aper_size, gatt_size, new_aper_size;
|
||||
unsigned aper_base, new_aper_base;
|
||||
struct pci_dev *dev;
|
||||
void *gatt;
|
||||
unsigned aper_base, new_aper_base;
|
||||
unsigned aper_size, gatt_size, new_aper_size;
|
||||
int i;
|
||||
|
||||
printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
|
||||
|
|
@ -509,75 +550,77 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
|
|||
dev = NULL;
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
dev = k8_northbridges[i];
|
||||
new_aper_base = read_aperture(dev, &new_aper_size);
|
||||
if (!new_aper_base)
|
||||
goto nommu;
|
||||
|
||||
if (!aper_base) {
|
||||
new_aper_base = read_aperture(dev, &new_aper_size);
|
||||
if (!new_aper_base)
|
||||
goto nommu;
|
||||
|
||||
if (!aper_base) {
|
||||
aper_size = new_aper_size;
|
||||
aper_base = new_aper_base;
|
||||
}
|
||||
if (aper_size != new_aper_size || aper_base != new_aper_base)
|
||||
}
|
||||
if (aper_size != new_aper_size || aper_base != new_aper_base)
|
||||
goto nommu;
|
||||
}
|
||||
if (!aper_base)
|
||||
goto nommu;
|
||||
goto nommu;
|
||||
info->aper_base = aper_base;
|
||||
info->aper_size = aper_size>>20;
|
||||
info->aper_size = aper_size >> 20;
|
||||
|
||||
gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
|
||||
gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
|
||||
if (!gatt)
|
||||
gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
|
||||
gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
|
||||
if (!gatt)
|
||||
panic("Cannot allocate GATT table");
|
||||
if (change_page_attr_addr((unsigned long)gatt, gatt_size >> PAGE_SHIFT, PAGE_KERNEL_NOCACHE))
|
||||
if (change_page_attr_addr((unsigned long)gatt, gatt_size >> PAGE_SHIFT,
|
||||
PAGE_KERNEL_NOCACHE))
|
||||
panic("Could not set GART PTEs to uncacheable pages");
|
||||
global_flush_tlb();
|
||||
|
||||
memset(gatt, 0, gatt_size);
|
||||
memset(gatt, 0, gatt_size);
|
||||
agp_gatt_table = gatt;
|
||||
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
u32 ctl;
|
||||
u32 gatt_reg;
|
||||
u32 gatt_reg;
|
||||
u32 ctl;
|
||||
|
||||
dev = k8_northbridges[i];
|
||||
gatt_reg = __pa(gatt) >> 12;
|
||||
gatt_reg <<= 4;
|
||||
gatt_reg = __pa(gatt) >> 12;
|
||||
gatt_reg <<= 4;
|
||||
pci_write_config_dword(dev, 0x98, gatt_reg);
|
||||
pci_read_config_dword(dev, 0x90, &ctl);
|
||||
pci_read_config_dword(dev, 0x90, &ctl);
|
||||
|
||||
ctl |= 1;
|
||||
ctl &= ~((1<<4) | (1<<5));
|
||||
|
||||
pci_write_config_dword(dev, 0x90, ctl);
|
||||
pci_write_config_dword(dev, 0x90, ctl);
|
||||
}
|
||||
flush_gart();
|
||||
|
||||
printk("PCI-DMA: aperture base @ %x size %u KB\n",aper_base, aper_size>>10);
|
||||
|
||||
printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
|
||||
aper_base, aper_size>>10);
|
||||
return 0;
|
||||
|
||||
nommu:
|
||||
/* Should not happen anymore */
|
||||
/* Should not happen anymore */
|
||||
printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
|
||||
KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n");
|
||||
return -1;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern int agp_amd64_init(void);
|
||||
|
||||
static const struct dma_mapping_ops gart_dma_ops = {
|
||||
.mapping_error = NULL,
|
||||
.map_single = gart_map_single,
|
||||
.map_simple = gart_map_simple,
|
||||
.unmap_single = gart_unmap_single,
|
||||
.sync_single_for_cpu = NULL,
|
||||
.sync_single_for_device = NULL,
|
||||
.sync_single_range_for_cpu = NULL,
|
||||
.sync_single_range_for_device = NULL,
|
||||
.sync_sg_for_cpu = NULL,
|
||||
.sync_sg_for_device = NULL,
|
||||
.map_sg = gart_map_sg,
|
||||
.unmap_sg = gart_unmap_sg,
|
||||
.mapping_error = NULL,
|
||||
.map_single = gart_map_single,
|
||||
.map_simple = gart_map_simple,
|
||||
.unmap_single = gart_unmap_single,
|
||||
.sync_single_for_cpu = NULL,
|
||||
.sync_single_for_device = NULL,
|
||||
.sync_single_range_for_cpu = NULL,
|
||||
.sync_single_range_for_device = NULL,
|
||||
.sync_sg_for_cpu = NULL,
|
||||
.sync_sg_for_device = NULL,
|
||||
.map_sg = gart_map_sg,
|
||||
.unmap_sg = gart_unmap_sg,
|
||||
};
|
||||
|
||||
void gart_iommu_shutdown(void)
|
||||
|
|
@ -588,23 +631,23 @@ void gart_iommu_shutdown(void)
|
|||
if (no_agp && (dma_ops != &gart_dma_ops))
|
||||
return;
|
||||
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
u32 ctl;
|
||||
for (i = 0; i < num_k8_northbridges; i++) {
|
||||
u32 ctl;
|
||||
|
||||
dev = k8_northbridges[i];
|
||||
pci_read_config_dword(dev, 0x90, &ctl);
|
||||
dev = k8_northbridges[i];
|
||||
pci_read_config_dword(dev, 0x90, &ctl);
|
||||
|
||||
ctl &= ~1;
|
||||
ctl &= ~1;
|
||||
|
||||
pci_write_config_dword(dev, 0x90, ctl);
|
||||
}
|
||||
pci_write_config_dword(dev, 0x90, ctl);
|
||||
}
|
||||
}
|
||||
|
||||
void __init gart_iommu_init(void)
|
||||
{
|
||||
{
|
||||
struct agp_kern_info info;
|
||||
unsigned long aper_size;
|
||||
unsigned long iommu_start;
|
||||
unsigned long aper_size;
|
||||
unsigned long scratch;
|
||||
long i;
|
||||
|
||||
|
|
@ -614,14 +657,14 @@ void __init gart_iommu_init(void)
|
|||
}
|
||||
|
||||
#ifndef CONFIG_AGP_AMD64
|
||||
no_agp = 1;
|
||||
no_agp = 1;
|
||||
#else
|
||||
/* Makefile puts PCI initialization via subsys_initcall first. */
|
||||
/* Add other K8 AGP bridge drivers here */
|
||||
no_agp = no_agp ||
|
||||
(agp_amd64_init() < 0) ||
|
||||
no_agp = no_agp ||
|
||||
(agp_amd64_init() < 0) ||
|
||||
(agp_copy_info(agp_bridge, &info) < 0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if (swiotlb)
|
||||
return;
|
||||
|
|
@ -643,77 +686,78 @@ void __init gart_iommu_init(void)
|
|||
}
|
||||
|
||||
printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
|
||||
aper_size = info.aper_size * 1024 * 1024;
|
||||
iommu_size = check_iommu_size(info.aper_base, aper_size);
|
||||
iommu_pages = iommu_size >> PAGE_SHIFT;
|
||||
aper_size = info.aper_size * 1024 * 1024;
|
||||
iommu_size = check_iommu_size(info.aper_base, aper_size);
|
||||
iommu_pages = iommu_size >> PAGE_SHIFT;
|
||||
|
||||
iommu_gart_bitmap = (void*)__get_free_pages(GFP_KERNEL,
|
||||
get_order(iommu_pages/8));
|
||||
if (!iommu_gart_bitmap)
|
||||
panic("Cannot allocate iommu bitmap\n");
|
||||
iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
|
||||
get_order(iommu_pages/8));
|
||||
if (!iommu_gart_bitmap)
|
||||
panic("Cannot allocate iommu bitmap\n");
|
||||
memset(iommu_gart_bitmap, 0, iommu_pages/8);
|
||||
|
||||
#ifdef CONFIG_IOMMU_LEAK
|
||||
if (leak_trace) {
|
||||
iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
|
||||
if (leak_trace) {
|
||||
iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
|
||||
get_order(iommu_pages*sizeof(void *)));
|
||||
if (iommu_leak_tab)
|
||||
memset(iommu_leak_tab, 0, iommu_pages * 8);
|
||||
if (iommu_leak_tab)
|
||||
memset(iommu_leak_tab, 0, iommu_pages * 8);
|
||||
else
|
||||
printk("PCI-DMA: Cannot allocate leak trace area\n");
|
||||
}
|
||||
printk(KERN_DEBUG
|
||||
"PCI-DMA: Cannot allocate leak trace area\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
/*
|
||||
* Out of IOMMU space handling.
|
||||
* Reserve some invalid pages at the beginning of the GART.
|
||||
*/
|
||||
set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
|
||||
* Reserve some invalid pages at the beginning of the GART.
|
||||
*/
|
||||
set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
|
||||
|
||||
agp_memory_reserved = iommu_size;
|
||||
agp_memory_reserved = iommu_size;
|
||||
printk(KERN_INFO
|
||||
"PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
|
||||
iommu_size>>20);
|
||||
iommu_size >> 20);
|
||||
|
||||
iommu_start = aper_size - iommu_size;
|
||||
iommu_bus_base = info.aper_base + iommu_start;
|
||||
iommu_start = aper_size - iommu_size;
|
||||
iommu_bus_base = info.aper_base + iommu_start;
|
||||
bad_dma_address = iommu_bus_base;
|
||||
iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Unmap the IOMMU part of the GART. The alias of the page is
|
||||
* always mapped with cache enabled and there is no full cache
|
||||
* coherency across the GART remapping. The unmapping avoids
|
||||
* automatic prefetches from the CPU allocating cache lines in
|
||||
* there. All CPU accesses are done via the direct mapping to
|
||||
* the backing memory. The GART address is only used by PCI
|
||||
* devices.
|
||||
* devices.
|
||||
*/
|
||||
clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size);
|
||||
|
||||
/*
|
||||
* Try to workaround a bug (thanks to BenH)
|
||||
* Set unmapped entries to a scratch page instead of 0.
|
||||
/*
|
||||
* Try to workaround a bug (thanks to BenH)
|
||||
* Set unmapped entries to a scratch page instead of 0.
|
||||
* Any prefetches that hit unmapped entries won't get an bus abort
|
||||
* then.
|
||||
*/
|
||||
scratch = get_zeroed_page(GFP_KERNEL);
|
||||
if (!scratch)
|
||||
scratch = get_zeroed_page(GFP_KERNEL);
|
||||
if (!scratch)
|
||||
panic("Cannot allocate iommu scratch page");
|
||||
gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
|
||||
for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
|
||||
for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
|
||||
iommu_gatt_base[i] = gart_unmapped_entry;
|
||||
|
||||
flush_gart();
|
||||
dma_ops = &gart_dma_ops;
|
||||
}
|
||||
}
|
||||
|
||||
void __init gart_parse_options(char *p)
|
||||
{
|
||||
int arg;
|
||||
|
||||
#ifdef CONFIG_IOMMU_LEAK
|
||||
if (!strncmp(p,"leak",4)) {
|
||||
if (!strncmp(p, "leak", 4)) {
|
||||
leak_trace = 1;
|
||||
p += 4;
|
||||
if (*p == '=') ++p;
|
||||
|
|
@ -723,18 +767,18 @@ void __init gart_parse_options(char *p)
|
|||
#endif
|
||||
if (isdigit(*p) && get_option(&p, &arg))
|
||||
iommu_size = arg;
|
||||
if (!strncmp(p, "fullflush",8))
|
||||
if (!strncmp(p, "fullflush", 8))
|
||||
iommu_fullflush = 1;
|
||||
if (!strncmp(p, "nofullflush",11))
|
||||
if (!strncmp(p, "nofullflush", 11))
|
||||
iommu_fullflush = 0;
|
||||
if (!strncmp(p,"noagp",5))
|
||||
if (!strncmp(p, "noagp", 5))
|
||||
no_agp = 1;
|
||||
if (!strncmp(p, "noaperture",10))
|
||||
if (!strncmp(p, "noaperture", 10))
|
||||
fix_aperture = 0;
|
||||
/* duplicated from pci-dma.c */
|
||||
if (!strncmp(p,"force",5))
|
||||
if (!strncmp(p, "force", 5))
|
||||
gart_iommu_aperture_allowed = 1;
|
||||
if (!strncmp(p,"allowed",7))
|
||||
if (!strncmp(p, "allowed", 7))
|
||||
gart_iommu_aperture_allowed = 1;
|
||||
if (!strncmp(p, "memaper", 7)) {
|
||||
fallback_aper_force = 1;
|
||||
|
|
|
|||
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