Merge branch 'stmp' into devel
This commit is contained in:
Russell King
Russell King
Коммит
0609996100
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@ -298,6 +298,19 @@ config ARCH_MXC
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help
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Support for Freescale MXC/iMX-based family of processors
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config ARCH_STMP3XXX
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bool "Freescale STMP3xxx"
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select CPU_ARM926T
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select HAVE_CLK
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select COMMON_CLKDEV
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
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select USB_ARCH_HAS_EHCI
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help
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Support for systems based on the Freescale 3xxx CPUs.
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config ARCH_NETX
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bool "Hilscher NetX based"
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select CPU_ARM926T
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@ -673,6 +686,8 @@ source "arch/arm/mach-s3c6400/Kconfig"
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source "arch/arm/mach-s3c6410/Kconfig"
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endif
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source "arch/arm/plat-stmp3xxx/Kconfig"
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source "arch/arm/mach-lh7a40x/Kconfig"
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source "arch/arm/mach-h720x/Kconfig"
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@ -152,6 +152,8 @@ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
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machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
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machine-$(CONFIG_ARCH_SA1100) := sa1100
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machine-$(CONFIG_ARCH_SHARK) := shark
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machine-$(CONFIG_ARCH_STMP378X) := stmp378x
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machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
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machine-$(CONFIG_ARCH_VERSATILE) := versatile
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machine-$(CONFIG_ARCH_W90X900) := w90x900
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machine-$(CONFIG_FOOTBRIDGE) := footbridge
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@ -165,6 +167,7 @@ plat-$(CONFIG_PLAT_ORION) := orion
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plat-$(CONFIG_PLAT_PXA) := pxa
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plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
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plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
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plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
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ifeq ($(CONFIG_ARCH_EBSA110),y)
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# This is what happens if you forget the IOCS16 line.
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,2 @@
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obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
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obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
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@ -0,0 +1,3 @@
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zreladdr-y := 0x40008000
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params_phys-y := 0x40000100
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initrd_phys-y := 0x40800000
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@ -0,0 +1,35 @@
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/*
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* Low-level IRQ helper macros for Freescale STMP378X
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*
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* Embedded Alley Solutions, Inc <source@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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||||
* Version 2 or later at the following locations:
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||||
*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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.macro disable_fiq
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov \base, #0xf0000000 @ vm address of IRQ controller
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ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
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cmp \irqnr, #0x7f
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moveqs \irqnr, #0 @ Zero flag set for no IRQ
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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@ -0,0 +1,95 @@
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/*
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* Freescale STMP378X interrupts
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*
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* Copyright (C) 2005 Sigmatel Inc
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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||||
* Version 2 or later at the following locations:
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||||
*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#define IRQ_DEBUG_UART 0
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#define IRQ_COMMS_RX 1
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#define IRQ_COMMS_TX 1
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#define IRQ_SSP2_ERROR 2
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#define IRQ_VDD5V 3
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#define IRQ_HEADPHONE_SHORT 4
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#define IRQ_DAC_DMA 5
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#define IRQ_DAC_ERROR 6
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#define IRQ_ADC_DMA 7
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#define IRQ_ADC_ERROR 8
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#define IRQ_SPDIF_DMA 9
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#define IRQ_SAIF2_DMA 9
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#define IRQ_SPDIF_ERROR 10
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#define IRQ_SAIF1_IRQ 10
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#define IRQ_SAIF2_IRQ 10
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#define IRQ_USB_CTRL 11
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#define IRQ_USB_WAKEUP 12
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#define IRQ_GPMI_DMA 13
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#define IRQ_SSP1_DMA 14
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#define IRQ_SSP_ERROR 15
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#define IRQ_GPIO0 16
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#define IRQ_GPIO1 17
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#define IRQ_GPIO2 18
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#define IRQ_SAIF1_DMA 19
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#define IRQ_SSP2_DMA 20
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#define IRQ_ECC8_IRQ 21
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#define IRQ_RTC_ALARM 22
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#define IRQ_UARTAPP_TX_DMA 23
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#define IRQ_UARTAPP_INTERNAL 24
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#define IRQ_UARTAPP_RX_DMA 25
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#define IRQ_I2C_DMA 26
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#define IRQ_I2C_ERROR 27
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#define IRQ_TIMER0 28
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#define IRQ_TIMER1 29
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#define IRQ_TIMER2 30
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#define IRQ_TIMER3 31
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#define IRQ_BATT_BRNOUT 32
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#define IRQ_VDDD_BRNOUT 33
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#define IRQ_VDDIO_BRNOUT 34
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#define IRQ_VDD18_BRNOUT 35
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#define IRQ_TOUCH_DETECT 36
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#define IRQ_LRADC_CH0 37
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#define IRQ_LRADC_CH1 38
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#define IRQ_LRADC_CH2 39
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#define IRQ_LRADC_CH3 40
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#define IRQ_LRADC_CH4 41
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#define IRQ_LRADC_CH5 42
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#define IRQ_LRADC_CH6 43
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#define IRQ_LRADC_CH7 44
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#define IRQ_LCDIF_DMA 45
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#define IRQ_LCDIF_ERROR 46
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#define IRQ_DIGCTL_DEBUG_TRAP 47
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#define IRQ_RTC_1MSEC 48
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#define IRQ_DRI_DMA 49
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#define IRQ_DRI_ATTENTION 50
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#define IRQ_GPMI_ATTENTION 51
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#define IRQ_IR 52
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#define IRQ_DCP_VMI 53
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#define IRQ_DCP 54
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#define IRQ_BCH 56
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#define IRQ_PXP 57
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#define IRQ_UARTAPP2_TX_DMA 58
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#define IRQ_UARTAPP2_INTERNAL 59
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#define IRQ_UARTAPP2_RX_DMA 60
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#define IRQ_VDAC_DETECT 61
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#define IRQ_VDD5V_DROOP 64
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#define IRQ_DCDC4P2_BO 65
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#define NR_REAL_IRQS 128
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#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
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/* All interrupts are FIQ capable */
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#define FIQ_START IRQ_DEBUG_UART
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/* Hard disk IRQ is a GPMI attention IRQ */
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#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
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@ -0,0 +1,151 @@
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/*
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* Freescale STMP378X SoC pin multiplexing
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*
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* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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||||
*/
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||||
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||||
/*
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||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ASM_ARCH_PINS_H
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#define __ASM_ARCH_PINS_H
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/*
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* Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
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* interface this pin belongs to.
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*/
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/* Bank 0 */
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#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
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#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
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#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
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#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
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#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
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#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
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#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
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#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
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#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
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#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
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#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
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#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
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#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
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#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
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#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
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#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
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#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
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#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
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#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
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#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
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#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
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#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
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#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
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#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
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#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
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#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
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#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
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#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
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#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
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#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
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#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
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#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
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/* Bank 1 */
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#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
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#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
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#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
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#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
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#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
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#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
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#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
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#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
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#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
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#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
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#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
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#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
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#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
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#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
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#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
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#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
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#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
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#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
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#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
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#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
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#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
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#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
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#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
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||||
#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
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||||
#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
|
||||
#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
|
||||
#define PINID_PWM0 STMP3XXX_PINID(1, 26)
|
||||
#define PINID_PWM1 STMP3XXX_PINID(1, 27)
|
||||
#define PINID_PWM2 STMP3XXX_PINID(1, 28)
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||||
#define PINID_PWM3 STMP3XXX_PINID(1, 29)
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||||
#define PINID_PWM4 STMP3XXX_PINID(1, 30)
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||||
|
||||
/* Bank 2 */
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||||
#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
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||||
#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
|
||||
#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
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||||
#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
|
||||
#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
|
||||
#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
|
||||
#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
|
||||
#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
|
||||
#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
|
||||
#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
|
||||
#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
|
||||
#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
|
||||
#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
|
||||
#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
|
||||
#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
|
||||
#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
|
||||
#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
|
||||
#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
|
||||
#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
|
||||
#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
|
||||
#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
|
||||
#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
|
||||
#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
|
||||
#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
|
||||
#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
|
||||
#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
|
||||
#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
|
||||
#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
|
||||
#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
|
||||
#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
|
||||
#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
|
||||
#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
|
||||
|
||||
/* Bank 3 */
|
||||
#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
|
||||
#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
|
||||
#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
|
||||
#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
|
||||
#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
|
||||
#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
|
||||
#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
|
||||
#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
|
||||
#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
|
||||
#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
|
||||
#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
|
||||
#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
|
||||
#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
|
||||
#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
|
||||
#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
|
||||
#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
|
||||
#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
|
||||
#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
|
||||
#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
|
||||
#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
|
||||
#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
|
||||
#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
|
||||
|
||||
#endif /* __ASM_ARCH_PINS_H */
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* stmp378x: APBH register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_APBH
|
||||
#define _MACH_REGS_APBH
|
||||
|
||||
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
|
||||
#define REGS_APBH_PHYS 0x80004000
|
||||
#define REGS_APBH_SIZE 0x2000
|
||||
|
||||
#define HW_APBH_CTRL0 0x0
|
||||
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
|
||||
#define BP_APBH_CTRL0_RESET_CHANNEL 16
|
||||
#define BM_APBH_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBH_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_APBH_CTRL1 0x10
|
||||
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
|
||||
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
|
||||
|
||||
#define HW_APBH_CTRL2 0x20
|
||||
|
||||
#define HW_APBH_DEVSEL 0x30
|
||||
|
||||
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_NXTCMDAR 0x50
|
||||
|
||||
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
|
||||
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
|
||||
#define BM_APBH_CHn_CMD_COMMAND 0x00000003
|
||||
#define BP_APBH_CHn_CMD_COMMAND 0
|
||||
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
|
||||
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
|
||||
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBH_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBH_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_SEMA 0x80
|
||||
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBH_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* stmp378x: APBX register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_APBX
|
||||
#define _MACH_REGS_APBX
|
||||
|
||||
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
|
||||
#define REGS_APBX_PHYS 0x80024000
|
||||
#define REGS_APBX_SIZE 0x2000
|
||||
|
||||
#define HW_APBX_CTRL0 0x0
|
||||
#define BM_APBX_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBX_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_APBX_CTRL1 0x10
|
||||
|
||||
#define HW_APBX_CTRL2 0x20
|
||||
|
||||
#define HW_APBX_CHANNEL_CTRL 0x30
|
||||
#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
|
||||
#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
|
||||
|
||||
#define HW_APBX_DEVSEL 0x40
|
||||
|
||||
#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_NXTCMDAR 0x110
|
||||
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
|
||||
#define BP_APBX_CHn_CMD_COMMAND 0
|
||||
#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
|
||||
#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
|
||||
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
|
||||
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBX_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBX_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_BAR 0x130
|
||||
|
||||
#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_SEMA 0x140
|
||||
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBX_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* stmp378x: AUDIOIN register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
|
||||
#define REGS_AUDIOIN_PHYS 0x8004C000
|
||||
#define REGS_AUDIOIN_SIZE 0x2000
|
||||
|
||||
#define HW_AUDIOIN_CTRL 0x0
|
||||
#define BM_AUDIOIN_CTRL_RUN 0x00000001
|
||||
#define BP_AUDIOIN_CTRL_RUN 0
|
||||
#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
|
||||
#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
|
||||
#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_AUDIOIN_STAT 0x10
|
||||
|
||||
#define HW_AUDIOIN_ADCSRR 0x20
|
||||
|
||||
#define HW_AUDIOIN_ADCVOLUME 0x30
|
||||
#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
|
||||
#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
|
||||
#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
|
||||
#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
|
||||
|
||||
#define HW_AUDIOIN_ADCDEBUG 0x40
|
||||
|
||||
#define HW_AUDIOIN_ADCVOL 0x50
|
||||
#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
|
||||
#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
|
||||
#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
|
||||
#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
|
||||
#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
|
||||
#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
|
||||
#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
|
||||
#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
|
||||
#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
|
||||
|
||||
#define HW_AUDIOIN_MICLINE 0x60
|
||||
|
||||
#define HW_AUDIOIN_ANACLKCTRL 0x70
|
||||
#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
|
||||
|
||||
#define HW_AUDIOIN_DATA 0x80
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* stmp378x: AUDIOOUT register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
|
||||
#define REGS_AUDIOOUT_PHYS 0x80048000
|
||||
#define REGS_AUDIOOUT_SIZE 0x2000
|
||||
|
||||
#define HW_AUDIOOUT_CTRL 0x0
|
||||
#define BM_AUDIOOUT_CTRL_RUN 0x00000001
|
||||
#define BP_AUDIOOUT_CTRL_RUN 0
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
|
||||
#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
|
||||
#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_AUDIOOUT_STAT 0x10
|
||||
|
||||
#define HW_AUDIOOUT_DACSRR 0x20
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_INT 16
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
|
||||
#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
|
||||
#define BP_AUDIOOUT_DACSRR_BASEMULT 28
|
||||
|
||||
#define HW_AUDIOOUT_DACVOLUME 0x30
|
||||
#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
|
||||
#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
|
||||
#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_DACDEBUG 0x40
|
||||
|
||||
#define HW_AUDIOOUT_HPVOL 0x50
|
||||
#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
|
||||
#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_PWRDN 0x70
|
||||
#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
|
||||
#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
|
||||
#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
|
||||
#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
|
||||
#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
|
||||
#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
|
||||
#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
|
||||
|
||||
#define HW_AUDIOOUT_REFCTRL 0x80
|
||||
#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
|
||||
#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
|
||||
#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
|
||||
#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
|
||||
#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
|
||||
#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
|
||||
#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
|
||||
#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
|
||||
#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
|
||||
#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
|
||||
#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
|
||||
#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
|
||||
#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_ANACTRL 0x90
|
||||
#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
|
||||
#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
|
||||
|
||||
#define HW_AUDIOOUT_TEST 0xA0
|
||||
#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
|
||||
#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
|
||||
|
||||
#define HW_AUDIOOUT_BISTCTRL 0xB0
|
||||
|
||||
#define HW_AUDIOOUT_BISTSTAT0 0xC0
|
||||
|
||||
#define HW_AUDIOOUT_BISTSTAT1 0xD0
|
||||
|
||||
#define HW_AUDIOOUT_ANACLKCTRL 0xE0
|
||||
#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
|
||||
|
||||
#define HW_AUDIOOUT_DATA 0xF0
|
||||
|
||||
#define HW_AUDIOOUT_SPEAKERCTRL 0x100
|
||||
#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
|
||||
|
||||
#define HW_AUDIOOUT_VERSION 0x200
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* stmp378x: BCH register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
|
||||
#define REGS_BCH_PHYS 0x8000A000
|
||||
#define REGS_BCH_SIZE 0x2000
|
||||
|
||||
#define HW_BCH_CTRL 0x0
|
||||
#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
|
||||
#define BP_BCH_CTRL_COMPLETE_IRQ 0
|
||||
#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
|
||||
|
||||
#define HW_BCH_STATUS0 0x10
|
||||
#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
|
||||
#define BM_BCH_STATUS0_CORRECTED 0x00000008
|
||||
#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
|
||||
#define BP_BCH_STATUS0_STATUS_BLK0 8
|
||||
#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
|
||||
#define BP_BCH_STATUS0_COMPLETED_CE 16
|
||||
|
||||
#define HW_BCH_LAYOUTSELECT 0x70
|
||||
|
||||
#define HW_BCH_FLASH0LAYOUT0 0x80
|
||||
#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
|
||||
#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
|
||||
#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
|
||||
#define BP_BCH_FLASH0LAYOUT0_ECC0 12
|
||||
#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
|
||||
#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
|
||||
#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
|
||||
#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
|
||||
#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
|
||||
#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
|
||||
#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
|
||||
#define BP_BCH_FLASH0LAYOUT1_ECCN 12
|
||||
#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
|
||||
#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
|
||||
|
||||
#define HW_BCH_BLOCKNAME 0x150
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* stmp378x: CLKCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_CLKCTRL
|
||||
#define _MACH_REGS_CLKCTRL
|
||||
|
||||
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
|
||||
#define REGS_CLKCTRL_PHYS 0x80040000
|
||||
#define REGS_CLKCTRL_SIZE 0x2000
|
||||
|
||||
#define HW_CLKCTRL_PLLCTRL0 0x0
|
||||
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
|
||||
|
||||
#define HW_CLKCTRL_CPU 0x20
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
|
||||
#define HW_CLKCTRL_HBUS 0x30
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
|
||||
|
||||
#define HW_CLKCTRL_XBUS 0x40
|
||||
|
||||
#define HW_CLKCTRL_XTAL 0x50
|
||||
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
|
||||
|
||||
#define HW_CLKCTRL_PIX 0x60
|
||||
#define BM_CLKCTRL_PIX_DIV 0x00000FFF
|
||||
#define BP_CLKCTRL_PIX_DIV 0
|
||||
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
|
||||
|
||||
#define HW_CLKCTRL_SSP 0x70
|
||||
|
||||
#define HW_CLKCTRL_GPMI 0x80
|
||||
|
||||
#define HW_CLKCTRL_SPDIF 0x90
|
||||
|
||||
#define HW_CLKCTRL_EMI 0xA0
|
||||
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
|
||||
#define BP_CLKCTRL_EMI_DIV_EMI 0
|
||||
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
|
||||
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
|
||||
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
|
||||
|
||||
#define HW_CLKCTRL_IR 0xB0
|
||||
|
||||
#define HW_CLKCTRL_SAIF 0xC0
|
||||
|
||||
#define HW_CLKCTRL_TV 0xD0
|
||||
|
||||
#define HW_CLKCTRL_ETM 0xE0
|
||||
|
||||
#define HW_CLKCTRL_FRAC 0xF0
|
||||
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
|
||||
#define BP_CLKCTRL_FRAC_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
|
||||
#define BP_CLKCTRL_FRAC_PIXFRAC 16
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
|
||||
|
||||
#define HW_CLKCTRL_FRAC1 0x100
|
||||
|
||||
#define HW_CLKCTRL_CLKSEQ 0x110
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
|
||||
|
||||
#define HW_CLKCTRL_RESET 0x120
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
#define BP_CLKCTRL_RESET_DIG 0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* stmp378x: DCP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
|
||||
#define REGS_DCP_PHYS 0x80028000
|
||||
#define REGS_DCP_SIZE 0x2000
|
||||
|
||||
#define HW_DCP_CTRL 0x0
|
||||
#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
|
||||
#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
|
||||
#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
|
||||
#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
|
||||
#define BM_DCP_CTRL_CLKGATE 0x40000000
|
||||
#define BM_DCP_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_DCP_STAT 0x10
|
||||
#define BM_DCP_STAT_IRQ 0x0000000F
|
||||
#define BP_DCP_STAT_IRQ 0
|
||||
|
||||
#define HW_DCP_CHANNELCTRL 0x20
|
||||
#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
|
||||
#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
|
||||
|
||||
#define HW_DCP_CONTEXT 0x50
|
||||
#define BM_DCP_PACKET1_INTERRUPT 0x00000001
|
||||
#define BP_DCP_PACKET1_INTERRUPT 0
|
||||
#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
|
||||
#define BM_DCP_PACKET1_CHAIN 0x00000004
|
||||
#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
|
||||
#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
|
||||
#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
|
||||
#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
|
||||
#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
|
||||
#define BM_DCP_PACKET1_OTP_KEY 0x00000400
|
||||
#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
|
||||
#define BM_DCP_PACKET1_HASH_INIT 0x00001000
|
||||
#define BM_DCP_PACKET1_HASH_TERM 0x00002000
|
||||
#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
|
||||
#define BP_DCP_PACKET2_CIPHER_SELECT 0
|
||||
#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
|
||||
#define BP_DCP_PACKET2_CIPHER_MODE 4
|
||||
#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
|
||||
#define BP_DCP_PACKET2_KEY_SELECT 8
|
||||
#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
|
||||
#define BP_DCP_PACKET2_HASH_SELECT 16
|
||||
#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
|
||||
#define BP_DCP_PACKET2_CIPHER_CFG 24
|
||||
|
||||
#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
|
||||
#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
|
||||
#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
|
||||
#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
|
||||
|
||||
#define HW_DCP_CHnCMDPTR 0x100
|
||||
|
||||
#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
|
||||
#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
|
||||
#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
|
||||
#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
|
||||
|
||||
#define HW_DCP_CHnSEMA 0x110
|
||||
#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
|
||||
#define BP_DCP_CHnSEMA_INCREMENT 0
|
||||
|
||||
#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
|
||||
#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
|
||||
#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
|
||||
#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
|
||||
|
||||
#define HW_DCP_CHnSTAT 0x120
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* stmp378x: DIGCTL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
|
||||
#define REGS_DIGCTL_PHYS 0x8001C000
|
||||
#define REGS_DIGCTL_SIZE 0x2000
|
||||
|
||||
#define HW_DIGCTL_CTRL 0x0
|
||||
#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
|
||||
|
||||
#define HW_DIGCTL_ARMCACHE 0x2B0
|
||||
#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
|
||||
#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
|
||||
#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
|
||||
#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
|
||||
#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
|
||||
#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
|
||||
#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
|
||||
#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
|
||||
#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
|
||||
#define BP_DIGCTL_ARMCACHE_VALID_SS 16
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* stmp378x: DRAM register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
|
||||
#define REGS_DRAM_PHYS 0x800E0000
|
||||
#define REGS_DRAM_SIZE 0x2000
|
||||
|
||||
#define HW_DRAM_CTL06 0x18
|
||||
|
||||
#define HW_DRAM_CTL08 0x20
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* stmp378x: DRI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
|
||||
#define REGS_DRI_PHYS 0x80074000
|
||||
#define REGS_DRI_SIZE 0x2000
|
||||
|
||||
#define HW_DRI_CTRL 0x0
|
||||
#define BM_DRI_CTRL_RUN 0x00000001
|
||||
#define BP_DRI_CTRL_RUN 0
|
||||
#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
|
||||
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
|
||||
#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
|
||||
#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
|
||||
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
|
||||
#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
|
||||
#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
|
||||
#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
|
||||
#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
|
||||
#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
|
||||
#define BM_DRI_CTRL_CLKGATE 0x40000000
|
||||
#define BM_DRI_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_DRI_TIMING 0x10
|
||||
#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
|
||||
#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
|
||||
#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
|
||||
#define BP_DRI_TIMING_PILOT_REP_RATE 16
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* stmp378x: ECC8 register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
|
||||
#define REGS_ECC8_PHYS 0x80008000
|
||||
#define REGS_ECC8_SIZE 0x2000
|
||||
|
||||
#define HW_ECC8_CTRL 0x0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
|
||||
#define BP_ECC8_CTRL_COMPLETE_IRQ 0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
|
||||
#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
|
||||
|
||||
#define HW_ECC8_STATUS0 0x10
|
||||
#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
|
||||
#define BM_ECC8_STATUS0_CORRECTED 0x00000008
|
||||
#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
|
||||
#define BP_ECC8_STATUS0_STATUS_AUX 8
|
||||
#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
|
||||
#define BP_ECC8_STATUS0_COMPLETED_CE 16
|
||||
|
||||
#define HW_ECC8_STATUS1 0x20
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* stmp378x: EMI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
|
||||
#define REGS_EMI_PHYS 0x80020000
|
||||
#define REGS_EMI_SIZE 0x2000
|
||||
|
||||
#define HW_EMI_STAT 0x10
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* stmp378x: GPMI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
|
||||
#define REGS_GPMI_PHYS 0x8000C000
|
||||
#define REGS_GPMI_SIZE 0x2000
|
||||
|
||||
#define HW_GPMI_CTRL0 0x0
|
||||
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_GPMI_CTRL0_XFER_COUNT 0
|
||||
#define BM_GPMI_CTRL0_CS 0x00300000
|
||||
#define BP_GPMI_CTRL0_CS 20
|
||||
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
|
||||
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
|
||||
#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
|
||||
#define BP_GPMI_CTRL0_ADDRESS 17
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
|
||||
#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
|
||||
#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
|
||||
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
|
||||
#define BP_GPMI_CTRL0_COMMAND_MODE 24
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
|
||||
#define BM_GPMI_CTRL0_RUN 0x20000000
|
||||
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_GPMI_CTRL0_SFTRST 0x80000000
|
||||
#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
|
||||
#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
|
||||
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
|
||||
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
|
||||
#define BP_GPMI_ECCCTRL_ECC_CMD 13
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
|
||||
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
|
||||
|
||||
#define HW_GPMI_CTRL1 0x60
|
||||
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
|
||||
#define BP_GPMI_CTRL1_GPMI_MODE 0
|
||||
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
|
||||
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
|
||||
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
|
||||
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
|
||||
#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
|
||||
#define BP_GPMI_CTRL1_RDN_DELAY 12
|
||||
#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
|
||||
|
||||
#define HW_GPMI_TIMING0 0x70
|
||||
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
|
||||
#define BP_GPMI_TIMING0_DATA_SETUP 0
|
||||
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
|
||||
#define BP_GPMI_TIMING0_DATA_HOLD 8
|
||||
#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
|
||||
#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
|
||||
|
||||
#define HW_GPMI_TIMING1 0x80
|
||||
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
|
||||
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* stmp378x: I2C register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
|
||||
#define REGS_I2C_PHYS 0x80058000
|
||||
#define REGS_I2C_SIZE 0x2000
|
||||
|
||||
#define HW_I2C_CTRL0 0x0
|
||||
#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_I2C_CTRL0_XFER_COUNT 0
|
||||
#define BM_I2C_CTRL0_DIRECTION 0x00010000
|
||||
#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
|
||||
#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
|
||||
#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
|
||||
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
|
||||
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
|
||||
#define BM_I2C_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_I2C_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_I2C_TIMING0 0x10
|
||||
|
||||
#define HW_I2C_TIMING1 0x20
|
||||
|
||||
#define HW_I2C_TIMING2 0x30
|
||||
|
||||
#define HW_I2C_CTRL1 0x40
|
||||
#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
|
||||
#define BP_I2C_CTRL1_SLAVE_IRQ 0
|
||||
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
|
||||
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
|
||||
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
|
||||
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
|
||||
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
|
||||
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
|
||||
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
|
||||
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
|
||||
|
||||
#define HW_I2C_VERSION 0x90
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* stmp378x: ICOLL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_ICOLL
|
||||
#define _MACH_REGS_ICOLL
|
||||
|
||||
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
|
||||
#define REGS_ICOLL_PHYS 0x80000000
|
||||
#define REGS_ICOLL_SIZE 0x2000
|
||||
|
||||
#define HW_ICOLL_VECTOR 0x0
|
||||
|
||||
#define HW_ICOLL_LEVELACK 0x10
|
||||
#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
|
||||
#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
|
||||
|
||||
#define HW_ICOLL_CTRL 0x20
|
||||
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
|
||||
#define BM_ICOLL_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_ICOLL_STAT 0x70
|
||||
|
||||
#define HW_ICOLL_INTERRUPTn 0x120
|
||||
|
||||
#define HW_ICOLL_INTERRUPTn 0x120
|
||||
#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* stmp378x: IR register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
|
||||
#define REGS_IR_PHYS 0x80078000
|
||||
#define REGS_IR_SIZE 0x2000
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* stmp378x: LCDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
|
||||
#define REGS_LCDIF_PHYS 0x80030000
|
||||
#define REGS_LCDIF_SIZE 0x2000
|
||||
|
||||
#define HW_LCDIF_CTRL 0x0
|
||||
#define BM_LCDIF_CTRL_RUN 0x00000001
|
||||
#define BP_LCDIF_CTRL_RUN 0
|
||||
#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
|
||||
#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
|
||||
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
|
||||
#define BP_LCDIF_CTRL_WORD_LENGTH 8
|
||||
#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
|
||||
#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
|
||||
#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
|
||||
#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
|
||||
#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
|
||||
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
|
||||
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
|
||||
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
|
||||
#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
|
||||
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
|
||||
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
|
||||
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
|
||||
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
|
||||
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_LCDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_LCDIF_CTRL1 0x10
|
||||
#define BM_LCDIF_CTRL1_RESET 0x00000001
|
||||
#define BP_LCDIF_CTRL1_RESET 0
|
||||
#define BM_LCDIF_CTRL1_MODE86 0x00000002
|
||||
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
|
||||
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
|
||||
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
|
||||
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
|
||||
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
|
||||
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
|
||||
#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
|
||||
#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
|
||||
|
||||
#define HW_LCDIF_TRANSFER_COUNT 0x20
|
||||
#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
|
||||
#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
|
||||
#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
|
||||
#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
|
||||
|
||||
#define HW_LCDIF_CUR_BUF 0x30
|
||||
|
||||
#define HW_LCDIF_NEXT_BUF 0x40
|
||||
|
||||
#define HW_LCDIF_TIMING 0x60
|
||||
|
||||
#define HW_LCDIF_VDCTRL0 0x70
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
|
||||
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
|
||||
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
|
||||
|
||||
#define HW_LCDIF_VDCTRL1 0x80
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
|
||||
|
||||
#define HW_LCDIF_VDCTRL2 0x90
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
|
||||
|
||||
#define HW_LCDIF_VDCTRL3 0xA0
|
||||
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
|
||||
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
|
||||
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
|
||||
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
|
||||
|
||||
#define HW_LCDIF_VDCTRL4 0xB0
|
||||
#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
|
||||
#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
|
||||
|
||||
#define HW_LCDIF_DVICTRL0 0xC0
|
||||
#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
|
||||
#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
|
||||
#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
|
||||
#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL1 0xD0
|
||||
#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
|
||||
#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
|
||||
#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
|
||||
#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL2 0xE0
|
||||
#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
|
||||
#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
|
||||
#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
|
||||
#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
|
||||
#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
|
||||
|
||||
#define HW_LCDIF_DVICTRL3 0xF0
|
||||
#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
|
||||
#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
|
||||
#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
|
||||
#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
|
||||
|
||||
#define HW_LCDIF_DVICTRL4 0x100
|
||||
#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
|
||||
#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
|
||||
#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
|
||||
#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
|
||||
#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
|
||||
#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
|
||||
#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
|
||||
#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF0 0x110
|
||||
#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
|
||||
#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
|
||||
#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF0_C0 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF1 0x120
|
||||
#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF1_C1 0
|
||||
#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF1_C2 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF2 0x130
|
||||
#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF2_C3 0
|
||||
#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF2_C4 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF3 0x140
|
||||
#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF3_C5 0
|
||||
#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF3_C6 16
|
||||
|
||||
#define HW_LCDIF_CSC_COEFF4 0x150
|
||||
#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
|
||||
#define BP_LCDIF_CSC_COEFF4_C7 0
|
||||
#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
|
||||
#define BP_LCDIF_CSC_COEFF4_C8 16
|
||||
|
||||
#define HW_LCDIF_CSC_OFFSET 0x160
|
||||
#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
|
||||
#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
|
||||
#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
|
||||
#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
|
||||
|
||||
#define HW_LCDIF_CSC_LIMIT 0x170
|
||||
#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
|
||||
#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
|
||||
#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
|
||||
#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
|
||||
#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
|
||||
#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
|
||||
#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
|
||||
#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
|
||||
|
||||
#define HW_LCDIF_STAT 0x1D0
|
||||
#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* stmp378x: LRADC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
|
||||
#define REGS_LRADC_PHYS 0x80050000
|
||||
#define REGS_LRADC_SIZE 0x2000
|
||||
|
||||
#define HW_LRADC_CTRL0 0x0
|
||||
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
|
||||
#define BP_LRADC_CTRL0_SCHEDULE 0
|
||||
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
|
||||
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
|
||||
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
|
||||
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
|
||||
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
|
||||
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
|
||||
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_LRADC_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_LRADC_CTRL1 0x10
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
|
||||
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
|
||||
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
|
||||
|
||||
#define HW_LRADC_CTRL2 0x20
|
||||
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
|
||||
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
|
||||
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
|
||||
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
|
||||
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
|
||||
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
|
||||
|
||||
#define HW_LRADC_CTRL3 0x30
|
||||
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
|
||||
#define BP_LRADC_CTRL3_CYCLE_TIME 8
|
||||
|
||||
#define HW_LRADC_STATUS 0x40
|
||||
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
|
||||
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
|
||||
|
||||
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
|
||||
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
|
||||
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
|
||||
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
|
||||
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
|
||||
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
|
||||
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
|
||||
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
|
||||
|
||||
#define HW_LRADC_CHn 0x50
|
||||
#define BM_LRADC_CHn_VALUE 0x0003FFFF
|
||||
#define BP_LRADC_CHn_VALUE 0
|
||||
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
|
||||
#define BP_LRADC_CHn_NUM_SAMPLES 24
|
||||
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
|
||||
|
||||
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
|
||||
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
|
||||
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
|
||||
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
|
||||
|
||||
#define HW_LRADC_DELAYn 0xD0
|
||||
#define BM_LRADC_DELAYn_DELAY 0x000007FF
|
||||
#define BP_LRADC_DELAYn_DELAY 0
|
||||
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
|
||||
#define BP_LRADC_DELAYn_LOOP_COUNT 11
|
||||
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
|
||||
#define BM_LRADC_DELAYn_KICK 0x00100000
|
||||
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
|
||||
|
||||
#define HW_LRADC_CTRL4 0x140
|
||||
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
|
||||
#define BP_LRADC_CTRL4_LRADC6SELECT 24
|
||||
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
|
||||
#define BP_LRADC_CTRL4_LRADC7SELECT 28
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* stmp378x: OCOTP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
|
||||
#define REGS_OCOTP_PHYS 0x8002C000
|
||||
#define REGS_OCOTP_SIZE 0x2000
|
||||
|
||||
#define HW_OCOTP_CTRL 0x0
|
||||
#define BM_OCOTP_CTRL_BUSY 0x00000100
|
||||
#define BM_OCOTP_CTRL_ERROR 0x00000200
|
||||
#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
|
||||
#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
|
||||
#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
|
||||
#define BP_OCOTP_CTRL_WR_UNLOCK 16
|
||||
|
||||
#define HW_OCOTP_DATA 0x10
|
||||
|
||||
#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
|
||||
#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
|
||||
#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
|
||||
#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
|
||||
|
||||
#define HW_OCOTP_CUSTn 0x20
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* stmp378x: PINCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_PINCTRL
|
||||
#define _MACH_REGS_PINCTRL
|
||||
|
||||
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
|
||||
#define REGS_PINCTRL_PHYS 0x80018000
|
||||
#define REGS_PINCTRL_SIZE 0x2000
|
||||
|
||||
#define HW_PINCTRL_MUXSEL0 0x100
|
||||
#define HW_PINCTRL_MUXSEL1 0x110
|
||||
#define HW_PINCTRL_MUXSEL2 0x120
|
||||
#define HW_PINCTRL_MUXSEL3 0x130
|
||||
#define HW_PINCTRL_MUXSEL4 0x140
|
||||
#define HW_PINCTRL_MUXSEL5 0x150
|
||||
#define HW_PINCTRL_MUXSEL6 0x160
|
||||
#define HW_PINCTRL_MUXSEL7 0x170
|
||||
|
||||
#define HW_PINCTRL_DRIVE0 0x200
|
||||
#define HW_PINCTRL_DRIVE1 0x210
|
||||
#define HW_PINCTRL_DRIVE2 0x220
|
||||
#define HW_PINCTRL_DRIVE3 0x230
|
||||
#define HW_PINCTRL_DRIVE4 0x240
|
||||
#define HW_PINCTRL_DRIVE5 0x250
|
||||
#define HW_PINCTRL_DRIVE6 0x260
|
||||
#define HW_PINCTRL_DRIVE7 0x270
|
||||
#define HW_PINCTRL_DRIVE8 0x280
|
||||
#define HW_PINCTRL_DRIVE9 0x290
|
||||
#define HW_PINCTRL_DRIVE10 0x2A0
|
||||
#define HW_PINCTRL_DRIVE11 0x2B0
|
||||
#define HW_PINCTRL_DRIVE12 0x2C0
|
||||
#define HW_PINCTRL_DRIVE13 0x2D0
|
||||
#define HW_PINCTRL_DRIVE14 0x2E0
|
||||
|
||||
#define HW_PINCTRL_PULL0 0x400
|
||||
#define HW_PINCTRL_PULL1 0x410
|
||||
#define HW_PINCTRL_PULL2 0x420
|
||||
#define HW_PINCTRL_PULL3 0x430
|
||||
|
||||
#define HW_PINCTRL_DOUT0 0x500
|
||||
#define HW_PINCTRL_DOUT1 0x510
|
||||
#define HW_PINCTRL_DOUT2 0x520
|
||||
|
||||
#define HW_PINCTRL_DIN0 0x600
|
||||
#define HW_PINCTRL_DIN1 0x610
|
||||
#define HW_PINCTRL_DIN2 0x620
|
||||
|
||||
#define HW_PINCTRL_DOE0 0x700
|
||||
#define HW_PINCTRL_DOE1 0x710
|
||||
#define HW_PINCTRL_DOE2 0x720
|
||||
|
||||
#define HW_PINCTRL_PIN2IRQ0 0x800
|
||||
#define HW_PINCTRL_PIN2IRQ1 0x810
|
||||
#define HW_PINCTRL_PIN2IRQ2 0x820
|
||||
|
||||
#define HW_PINCTRL_IRQEN0 0x900
|
||||
#define HW_PINCTRL_IRQEN1 0x910
|
||||
#define HW_PINCTRL_IRQEN2 0x920
|
||||
|
||||
#define HW_PINCTRL_IRQLEVEL0 0xA00
|
||||
#define HW_PINCTRL_IRQLEVEL1 0xA10
|
||||
#define HW_PINCTRL_IRQLEVEL2 0xA20
|
||||
|
||||
#define HW_PINCTRL_IRQPOL0 0xB00
|
||||
#define HW_PINCTRL_IRQPOL1 0xB10
|
||||
#define HW_PINCTRL_IRQPOL2 0xB20
|
||||
|
||||
#define HW_PINCTRL_IRQSTAT0 0xC00
|
||||
#define HW_PINCTRL_IRQSTAT1 0xC10
|
||||
#define HW_PINCTRL_IRQSTAT2 0xC20
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* stmp378x: POWER register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_POWER
|
||||
#define _MACH_REGS_POWER
|
||||
|
||||
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
|
||||
#define REGS_POWER_PHYS 0x80044000
|
||||
#define REGS_POWER_SIZE 0x2000
|
||||
|
||||
#define HW_POWER_CTRL 0x0
|
||||
#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
|
||||
#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
|
||||
#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
|
||||
#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
|
||||
#define BM_POWER_CTRL_CLKGATE 0x40000000
|
||||
|
||||
#define HW_POWER_5VCTRL 0x10
|
||||
#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
|
||||
|
||||
#define HW_POWER_MINPWR 0x20
|
||||
|
||||
#define HW_POWER_CHARGE 0x30
|
||||
|
||||
#define HW_POWER_VDDDCTRL 0x40
|
||||
|
||||
#define HW_POWER_VDDACTRL 0x50
|
||||
|
||||
#define HW_POWER_VDDIOCTRL 0x60
|
||||
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
|
||||
#define BP_POWER_VDDIOCTRL_TRG 0
|
||||
|
||||
#define HW_POWER_STS 0xC0
|
||||
#define BM_POWER_STS_VBUSVALID 0x00000002
|
||||
#define BM_POWER_STS_BVALID 0x00000004
|
||||
#define BM_POWER_STS_AVALID 0x00000008
|
||||
#define BM_POWER_STS_DC_OK 0x00000200
|
||||
|
||||
#define HW_POWER_RESET 0x100
|
||||
|
||||
#define HW_POWER_DEBUG 0x110
|
||||
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
|
||||
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
|
||||
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* stmp378x: PWM register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
|
||||
#define REGS_PWM_PHYS 0x80064000
|
||||
#define REGS_PWM_SIZE 0x2000
|
||||
|
||||
#define HW_PWM_CTRL 0x0
|
||||
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
|
||||
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
|
||||
|
||||
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
|
||||
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
|
||||
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
|
||||
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_ACTIVEn 0x10
|
||||
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
|
||||
#define BP_PWM_ACTIVEn_ACTIVE 0
|
||||
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
|
||||
#define BP_PWM_ACTIVEn_INACTIVE 16
|
||||
|
||||
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
|
||||
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
|
||||
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
|
||||
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_PERIODn 0x20
|
||||
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
|
||||
#define BP_PWM_PERIODn_PERIOD 0
|
||||
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
|
||||
#define BP_PWM_PERIODn_ACTIVE_STATE 16
|
||||
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
|
||||
#define BP_PWM_PERIODn_INACTIVE_STATE 18
|
||||
#define BM_PWM_PERIODn_CDIV 0x00700000
|
||||
#define BP_PWM_PERIODn_CDIV 20
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* stmp378x: PXP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
|
||||
#define REGS_PXP_PHYS 0x8002A000
|
||||
#define REGS_PXP_SIZE 0x2000
|
||||
|
||||
#define HW_PXP_CTRL 0x0
|
||||
#define BM_PXP_CTRL_ENABLE 0x00000001
|
||||
#define BP_PXP_CTRL_ENABLE 0
|
||||
#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
|
||||
#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
|
||||
#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
|
||||
#define BM_PXP_CTRL_ROTATE 0x00000300
|
||||
#define BP_PXP_CTRL_ROTATE 8
|
||||
#define BM_PXP_CTRL_HFLIP 0x00000400
|
||||
#define BM_PXP_CTRL_VFLIP 0x00000800
|
||||
#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
|
||||
#define BP_PXP_CTRL_S0_FORMAT 12
|
||||
#define BM_PXP_CTRL_SCALE 0x00040000
|
||||
#define BM_PXP_CTRL_CROP 0x00080000
|
||||
|
||||
#define HW_PXP_STAT 0x10
|
||||
#define BM_PXP_STAT_IRQ 0x00000001
|
||||
#define BP_PXP_STAT_IRQ 0
|
||||
|
||||
#define HW_PXP_RGBBUF 0x20
|
||||
|
||||
#define HW_PXP_RGBSIZE 0x40
|
||||
#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
|
||||
#define BP_PXP_RGBSIZE_HEIGHT 0
|
||||
#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
|
||||
#define BP_PXP_RGBSIZE_WIDTH 12
|
||||
|
||||
#define HW_PXP_S0BUF 0x50
|
||||
|
||||
#define HW_PXP_S0UBUF 0x60
|
||||
|
||||
#define HW_PXP_S0VBUF 0x70
|
||||
|
||||
#define HW_PXP_S0PARAM 0x80
|
||||
#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
|
||||
#define BP_PXP_S0PARAM_HEIGHT 0
|
||||
#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
|
||||
#define BP_PXP_S0PARAM_WIDTH 8
|
||||
#define BM_PXP_S0PARAM_YBASE 0x00FF0000
|
||||
#define BP_PXP_S0PARAM_YBASE 16
|
||||
#define BM_PXP_S0PARAM_XBASE 0xFF000000
|
||||
#define BP_PXP_S0PARAM_XBASE 24
|
||||
|
||||
#define HW_PXP_S0BACKGROUND 0x90
|
||||
|
||||
#define HW_PXP_S0CROP 0xA0
|
||||
#define BM_PXP_S0CROP_HEIGHT 0x000000FF
|
||||
#define BP_PXP_S0CROP_HEIGHT 0
|
||||
#define BM_PXP_S0CROP_WIDTH 0x0000FF00
|
||||
#define BP_PXP_S0CROP_WIDTH 8
|
||||
#define BM_PXP_S0CROP_YBASE 0x00FF0000
|
||||
#define BP_PXP_S0CROP_YBASE 16
|
||||
#define BM_PXP_S0CROP_XBASE 0xFF000000
|
||||
#define BP_PXP_S0CROP_XBASE 24
|
||||
|
||||
#define HW_PXP_S0SCALE 0xB0
|
||||
#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
|
||||
#define BP_PXP_S0SCALE_XSCALE 0
|
||||
#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
|
||||
#define BP_PXP_S0SCALE_YSCALE 16
|
||||
|
||||
#define HW_PXP_CSCCOEFF0 0xD0
|
||||
|
||||
#define HW_PXP_CSCCOEFF1 0xE0
|
||||
|
||||
#define HW_PXP_CSCCOEFF2 0xF0
|
||||
|
||||
#define HW_PXP_S0COLORKEYLOW 0x180
|
||||
|
||||
#define HW_PXP_S0COLORKEYHIGH 0x190
|
||||
|
||||
#define HW_PXP_OL0 (0x200 + 0 * 0x40)
|
||||
#define HW_PXP_OL1 (0x200 + 1 * 0x40)
|
||||
#define HW_PXP_OL2 (0x200 + 2 * 0x40)
|
||||
#define HW_PXP_OL3 (0x200 + 3 * 0x40)
|
||||
#define HW_PXP_OL4 (0x200 + 4 * 0x40)
|
||||
#define HW_PXP_OL5 (0x200 + 5 * 0x40)
|
||||
#define HW_PXP_OL6 (0x200 + 6 * 0x40)
|
||||
#define HW_PXP_OL7 (0x200 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLn 0x200
|
||||
|
||||
#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
|
||||
#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
|
||||
#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
|
||||
#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
|
||||
#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
|
||||
#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
|
||||
#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
|
||||
#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLnSIZE 0x210
|
||||
#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
|
||||
#define BP_PXP_OLnSIZE_HEIGHT 0
|
||||
#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
|
||||
#define BP_PXP_OLnSIZE_WIDTH 8
|
||||
|
||||
#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
|
||||
#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
|
||||
#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
|
||||
#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
|
||||
#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
|
||||
#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
|
||||
#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
|
||||
#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
|
||||
|
||||
#define HW_PXP_OLnPARAM 0x220
|
||||
#define BM_PXP_OLnPARAM_ENABLE 0x00000001
|
||||
#define BP_PXP_OLnPARAM_ENABLE 0
|
||||
#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
|
||||
#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
|
||||
#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
|
||||
#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
|
||||
#define BP_PXP_OLnPARAM_FORMAT 4
|
||||
#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
|
||||
#define BP_PXP_OLnPARAM_ALPHA 8
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* stmp378x: RTC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
|
||||
#define REGS_RTC_PHYS 0x8005C000
|
||||
#define REGS_RTC_SIZE 0x2000
|
||||
|
||||
#define HW_RTC_CTRL 0x0
|
||||
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
|
||||
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
|
||||
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
|
||||
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
|
||||
|
||||
#define HW_RTC_STAT 0x10
|
||||
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
|
||||
#define BP_RTC_STAT_NEW_REGS 8
|
||||
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
|
||||
#define BP_RTC_STAT_STALE_REGS 16
|
||||
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
|
||||
|
||||
#define HW_RTC_SECONDS 0x30
|
||||
|
||||
#define HW_RTC_ALARM 0x40
|
||||
|
||||
#define HW_RTC_WATCHDOG 0x50
|
||||
|
||||
#define HW_RTC_PERSISTENT0 0x60
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
|
||||
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
|
||||
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
|
||||
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
|
||||
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
|
||||
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
|
||||
|
||||
#define HW_RTC_PERSISTENT1 0x70
|
||||
#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
|
||||
#define BP_RTC_PERSISTENT1_GENERAL 0
|
||||
|
||||
#define HW_RTC_VERSION 0xD0
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* stmp378x: SAIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SAIF_SIZE 0x2000
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* stmp378x: SPDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
|
||||
#define REGS_SPDIF_PHYS 0x80054000
|
||||
#define REGS_SPDIF_SIZE 0x2000
|
||||
|
||||
#define HW_SPDIF_CTRL 0x0
|
||||
#define BM_SPDIF_CTRL_RUN 0x00000001
|
||||
#define BP_SPDIF_CTRL_RUN 0
|
||||
#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
|
||||
#define BM_SPDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_SPDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_SPDIF_STAT 0x10
|
||||
|
||||
#define HW_SPDIF_FRAMECTRL 0x20
|
||||
|
||||
#define HW_SPDIF_SRR 0x30
|
||||
#define BM_SPDIF_SRR_RATE 0x000FFFFF
|
||||
#define BP_SPDIF_SRR_RATE 0
|
||||
#define BM_SPDIF_SRR_BASEMULT 0x70000000
|
||||
#define BP_SPDIF_SRR_BASEMULT 28
|
||||
|
||||
#define HW_SPDIF_DEBUG 0x40
|
||||
|
||||
#define HW_SPDIF_DATA 0x50
|
||||
|
||||
#define HW_SPDIF_VERSION 0x60
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* stmp378x: SSP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
|
||||
#define REGS_SSP1_PHYS 0x80010000
|
||||
#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
|
||||
#define REGS_SSP2_PHYS 0x80034000
|
||||
#define REGS_SSP_SIZE 0x2000
|
||||
|
||||
#define HW_SSP_CTRL0 0x0
|
||||
#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_SSP_CTRL0_XFER_COUNT 0
|
||||
#define BM_SSP_CTRL0_ENABLE 0x00010000
|
||||
#define BM_SSP_CTRL0_GET_RESP 0x00020000
|
||||
#define BM_SSP_CTRL0_LONG_RESP 0x00080000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
|
||||
#define BP_SSP_CTRL0_BUS_WIDTH 22
|
||||
#define BM_SSP_CTRL0_DATA_XFER 0x01000000
|
||||
#define BM_SSP_CTRL0_READ 0x02000000
|
||||
#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
|
||||
#define BM_SSP_CTRL0_LOCK_CS 0x08000000
|
||||
#define BM_SSP_CTRL0_RUN 0x20000000
|
||||
#define BM_SSP_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_SSP_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_SSP_CMD0 0x10
|
||||
#define BM_SSP_CMD0_CMD 0x000000FF
|
||||
#define BP_SSP_CMD0_CMD 0
|
||||
#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
|
||||
#define BP_SSP_CMD0_BLOCK_COUNT 8
|
||||
#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
|
||||
#define BP_SSP_CMD0_BLOCK_SIZE 16
|
||||
#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
|
||||
#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
|
||||
#define BP_SSP_CMD1_CMD_ARG 0
|
||||
|
||||
#define HW_SSP_TIMING 0x50
|
||||
#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
|
||||
#define BP_SSP_TIMING_CLOCK_RATE 0
|
||||
#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
|
||||
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
|
||||
#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
|
||||
#define BP_SSP_TIMING_TIMEOUT 16
|
||||
|
||||
#define HW_SSP_CTRL1 0x60
|
||||
#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
|
||||
#define BP_SSP_CTRL1_SSP_MODE 0
|
||||
#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
|
||||
#define BP_SSP_CTRL1_WORD_LENGTH 4
|
||||
#define BM_SSP_CTRL1_POLARITY 0x00000200
|
||||
#define BM_SSP_CTRL1_PHASE 0x00000400
|
||||
#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
|
||||
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
|
||||
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
|
||||
#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
|
||||
|
||||
#define HW_SSP_DATA 0x70
|
||||
|
||||
#define HW_SSP_SDRESP0 0x80
|
||||
|
||||
#define HW_SSP_SDRESP1 0x90
|
||||
|
||||
#define HW_SSP_SDRESP2 0xA0
|
||||
|
||||
#define HW_SSP_SDRESP3 0xB0
|
||||
|
||||
#define HW_SSP_STATUS 0xC0
|
||||
#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
|
||||
#define BM_SSP_STATUS_TIMEOUT 0x00001000
|
||||
#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
|
||||
#define BM_SSP_STATUS_RESP_ERR 0x00008000
|
||||
#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
|
||||
#define BM_SSP_STATUS_CARD_DETECT 0x10000000
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* stmp378x: SYDMA register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
|
||||
#define REGS_SYDMA_PHYS 0x80026000
|
||||
#define REGS_SYDMA_SIZE 0x2000
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* stmp378x: TIMROT register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_TIMROT
|
||||
#define _MACH_REGS_TIMROT
|
||||
|
||||
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
|
||||
#define REGS_TIMROT_PHYS 0x80068000
|
||||
#define REGS_TIMROT_SIZE 0x2000
|
||||
|
||||
#define HW_TIMROT_ROTCTRL 0x0
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_A 0
|
||||
#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
|
||||
#define BP_TIMROT_ROTCTRL_SELECT_B 4
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
|
||||
#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
|
||||
#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
|
||||
#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
|
||||
#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
|
||||
#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
|
||||
#define BP_TIMROT_ROTCTRL_DIVIDER 16
|
||||
#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
|
||||
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
|
||||
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_TIMROT_ROTCOUNT 0x10
|
||||
#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
|
||||
#define BP_TIMROT_ROTCOUNT_UPDOWN 0
|
||||
|
||||
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCTRLn 0x20
|
||||
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
|
||||
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
||||
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
|
||||
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
|
||||
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
|
||||
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
|
||||
|
||||
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCOUNTn 0x30
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* stmp378x: TVENC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
|
||||
#define REGS_TVENC_PHYS 0x80038000
|
||||
#define REGS_TVENC_SIZE 0x2000
|
||||
|
||||
#define HW_TVENC_CTRL 0x0
|
||||
#define BM_TVENC_CTRL_CLKGATE 0x40000000
|
||||
#define BM_TVENC_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_TVENC_CONFIG 0x10
|
||||
#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
|
||||
#define BP_TVENC_CONFIG_ENCD_MODE 0
|
||||
#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
|
||||
#define BP_TVENC_CONFIG_SYNC_MODE 4
|
||||
#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
|
||||
#define BM_TVENC_CONFIG_CGAIN 0x0000C000
|
||||
#define BP_TVENC_CONFIG_CGAIN 14
|
||||
#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
|
||||
#define BP_TVENC_CONFIG_YGAIN_SEL 16
|
||||
#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
|
||||
|
||||
#define HW_TVENC_SYNCOFFSET 0x30
|
||||
|
||||
#define HW_TVENC_COLORSUB0 0xC0
|
||||
|
||||
#define HW_TVENC_COLORBURST 0x140
|
||||
#define BM_TVENC_COLORBURST_PBA 0x00FF0000
|
||||
#define BP_TVENC_COLORBURST_PBA 16
|
||||
#define BM_TVENC_COLORBURST_NBA 0xFF000000
|
||||
#define BP_TVENC_COLORBURST_NBA 24
|
||||
|
||||
#define HW_TVENC_MACROVISION0 0x150
|
||||
|
||||
#define HW_TVENC_MACROVISION1 0x160
|
||||
|
||||
#define HW_TVENC_MACROVISION2 0x170
|
||||
|
||||
#define HW_TVENC_MACROVISION3 0x180
|
||||
|
||||
#define HW_TVENC_MACROVISION4 0x190
|
||||
|
||||
#define HW_TVENC_DACCTRL 0x1A0
|
||||
#define BM_TVENC_DACCTRL_RVAL 0x00000070
|
||||
#define BP_TVENC_DACCTRL_RVAL 4
|
||||
#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
|
||||
#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
|
||||
#define BM_TVENC_DACCTRL_GAINUP 0x00040000
|
||||
#define BM_TVENC_DACCTRL_GAINDN 0x00080000
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* stmp378x: UARTAPP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
|
||||
#define REGS_UARTAPP1_PHYS 0x8006C000
|
||||
#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
|
||||
#define REGS_UARTAPP2_PHYS 0x8006E000
|
||||
#define REGS_UARTAPP_SIZE 0x2000
|
||||
|
||||
#define HW_UARTAPP_CTRL0 0x0
|
||||
#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL0_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
|
||||
#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
|
||||
#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
|
||||
#define BM_UARTAPP_CTRL0_RUN 0x20000000
|
||||
#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
|
||||
#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL1_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL1_RUN 0x10000000
|
||||
|
||||
#define HW_UARTAPP_CTRL2 0x20
|
||||
#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
|
||||
#define BP_UARTAPP_CTRL2_UARTEN 0
|
||||
#define BM_UARTAPP_CTRL2_TXE 0x00000100
|
||||
#define BM_UARTAPP_CTRL2_RXE 0x00000200
|
||||
#define BM_UARTAPP_CTRL2_RTS 0x00000800
|
||||
#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
|
||||
#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
|
||||
#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
|
||||
#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
|
||||
#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
|
||||
|
||||
#define HW_UARTAPP_LINECTRL 0x30
|
||||
#define BM_UARTAPP_LINECTRL_BRK 0x00000001
|
||||
#define BP_UARTAPP_LINECTRL_BRK 0
|
||||
#define BM_UARTAPP_LINECTRL_PEN 0x00000002
|
||||
#define BM_UARTAPP_LINECTRL_EPS 0x00000004
|
||||
#define BM_UARTAPP_LINECTRL_STP2 0x00000008
|
||||
#define BM_UARTAPP_LINECTRL_FEN 0x00000010
|
||||
#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
|
||||
#define BP_UARTAPP_LINECTRL_WLEN 5
|
||||
#define BM_UARTAPP_LINECTRL_SPS 0x00000080
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
|
||||
|
||||
#define HW_UARTAPP_INTR 0x50
|
||||
#define BM_UARTAPP_INTR_CTSMIS 0x00000002
|
||||
#define BM_UARTAPP_INTR_RTIS 0x00000040
|
||||
#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
|
||||
#define BM_UARTAPP_INTR_RXIEN 0x00100000
|
||||
#define BM_UARTAPP_INTR_RTIEN 0x00400000
|
||||
|
||||
#define HW_UARTAPP_DATA 0x60
|
||||
|
||||
#define HW_UARTAPP_STAT 0x70
|
||||
#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_STAT_RXCOUNT 0
|
||||
#define BM_UARTAPP_STAT_FERR 0x00010000
|
||||
#define BM_UARTAPP_STAT_PERR 0x00020000
|
||||
#define BM_UARTAPP_STAT_BERR 0x00040000
|
||||
#define BM_UARTAPP_STAT_OERR 0x00080000
|
||||
#define BM_UARTAPP_STAT_RXFE 0x01000000
|
||||
#define BM_UARTAPP_STAT_TXFF 0x02000000
|
||||
#define BM_UARTAPP_STAT_TXFE 0x08000000
|
||||
#define BM_UARTAPP_STAT_CTS 0x10000000
|
||||
|
||||
#define HW_UARTAPP_VERSION 0x90
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* stmp378x: UARTDBG register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
|
||||
#define REGS_UARTDBG_PHYS 0x80070000
|
||||
#define REGS_UARTDBG_SIZE 0x2000
|
||||
|
||||
#define HW_UARTDBGDR 0x00000000
|
||||
#define BP_UARTDBGDR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDR_RESERVED 12
|
||||
#define BM_UARTDBGDR_RESERVED 0x0000F000
|
||||
#define BF_UARTDBGDR_RESERVED(v) \
|
||||
(((v) << 12) & BM_UARTDBGDR_RESERVED)
|
||||
#define BM_UARTDBGDR_OE 0x00000800
|
||||
#define BM_UARTDBGDR_BE 0x00000400
|
||||
#define BM_UARTDBGDR_PE 0x00000200
|
||||
#define BM_UARTDBGDR_FE 0x00000100
|
||||
#define BP_UARTDBGDR_DATA 0
|
||||
#define BM_UARTDBGDR_DATA 0x000000FF
|
||||
#define BF_UARTDBGDR_DATA(v) \
|
||||
(((v) << 0) & BM_UARTDBGDR_DATA)
|
||||
#define HW_UARTDBGRSR_ECR 0x00000004
|
||||
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
|
||||
#define BP_UARTDBGRSR_ECR_EC 4
|
||||
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
|
||||
#define BF_UARTDBGRSR_ECR_EC(v) \
|
||||
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
|
||||
#define BM_UARTDBGRSR_ECR_OE 0x00000008
|
||||
#define BM_UARTDBGRSR_ECR_BE 0x00000004
|
||||
#define BM_UARTDBGRSR_ECR_PE 0x00000002
|
||||
#define BM_UARTDBGRSR_ECR_FE 0x00000001
|
||||
#define HW_UARTDBGFR 0x00000018
|
||||
#define BP_UARTDBGFR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGFR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
|
||||
#define BP_UARTDBGFR_RESERVED 9
|
||||
#define BM_UARTDBGFR_RESERVED 0x0000FE00
|
||||
#define BF_UARTDBGFR_RESERVED(v) \
|
||||
(((v) << 9) & BM_UARTDBGFR_RESERVED)
|
||||
#define BM_UARTDBGFR_RI 0x00000100
|
||||
#define BM_UARTDBGFR_TXFE 0x00000080
|
||||
#define BM_UARTDBGFR_RXFF 0x00000040
|
||||
#define BM_UARTDBGFR_TXFF 0x00000020
|
||||
#define BM_UARTDBGFR_RXFE 0x00000010
|
||||
#define BM_UARTDBGFR_BUSY 0x00000008
|
||||
#define BM_UARTDBGFR_DCD 0x00000004
|
||||
#define BM_UARTDBGFR_DSR 0x00000002
|
||||
#define BM_UARTDBGFR_CTS 0x00000001
|
||||
#define HW_UARTDBGILPR 0x00000020
|
||||
#define BP_UARTDBGILPR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
|
||||
#define BP_UARTDBGILPR_ILPDVSR 0
|
||||
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
|
||||
#define BF_UARTDBGILPR_ILPDVSR(v) \
|
||||
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
|
||||
#define HW_UARTDBGIBRD 0x00000024
|
||||
#define BP_UARTDBGIBRD_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
|
||||
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
|
||||
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
|
||||
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
|
||||
#define HW_UARTDBGFBRD 0x00000028
|
||||
#define BP_UARTDBGFBRD_UNAVAILABLE 8
|
||||
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGFBRD_RESERVED 6
|
||||
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
|
||||
#define BF_UARTDBGFBRD_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
|
||||
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
|
||||
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
|
||||
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
|
||||
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
|
||||
#define HW_UARTDBGLCR_H 0x0000002c
|
||||
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
|
||||
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
|
||||
#define BP_UARTDBGLCR_H_RESERVED 8
|
||||
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
|
||||
#define BF_UARTDBGLCR_H_RESERVED(v) \
|
||||
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
|
||||
#define BM_UARTDBGLCR_H_SPS 0x00000080
|
||||
#define BP_UARTDBGLCR_H_WLEN 5
|
||||
#define BM_UARTDBGLCR_H_WLEN 0x00000060
|
||||
#define BF_UARTDBGLCR_H_WLEN(v) \
|
||||
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
|
||||
#define BM_UARTDBGLCR_H_FEN 0x00000010
|
||||
#define BM_UARTDBGLCR_H_STP2 0x00000008
|
||||
#define BM_UARTDBGLCR_H_EPS 0x00000004
|
||||
#define BM_UARTDBGLCR_H_PEN 0x00000002
|
||||
#define BM_UARTDBGLCR_H_BRK 0x00000001
|
||||
#define HW_UARTDBGCR 0x00000030
|
||||
#define BP_UARTDBGCR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGCR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
|
||||
#define BM_UARTDBGCR_CTSEN 0x00008000
|
||||
#define BM_UARTDBGCR_RTSEN 0x00004000
|
||||
#define BM_UARTDBGCR_OUT2 0x00002000
|
||||
#define BM_UARTDBGCR_OUT1 0x00001000
|
||||
#define BM_UARTDBGCR_RTS 0x00000800
|
||||
#define BM_UARTDBGCR_DTR 0x00000400
|
||||
#define BM_UARTDBGCR_RXE 0x00000200
|
||||
#define BM_UARTDBGCR_TXE 0x00000100
|
||||
#define BM_UARTDBGCR_LBE 0x00000080
|
||||
#define BP_UARTDBGCR_RESERVED 3
|
||||
#define BM_UARTDBGCR_RESERVED 0x00000078
|
||||
#define BF_UARTDBGCR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGCR_RESERVED)
|
||||
#define BM_UARTDBGCR_SIRLP 0x00000004
|
||||
#define BM_UARTDBGCR_SIREN 0x00000002
|
||||
#define BM_UARTDBGCR_UARTEN 0x00000001
|
||||
#define HW_UARTDBGIFLS 0x00000034
|
||||
#define BP_UARTDBGIFLS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
|
||||
#define BP_UARTDBGIFLS_RESERVED 6
|
||||
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
|
||||
#define BF_UARTDBGIFLS_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
|
||||
#define BP_UARTDBGIFLS_RXIFLSEL 3
|
||||
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
|
||||
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
|
||||
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
|
||||
#define BP_UARTDBGIFLS_TXIFLSEL 0
|
||||
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
|
||||
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
|
||||
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
|
||||
#define HW_UARTDBGIMSC 0x00000038
|
||||
#define BP_UARTDBGIMSC_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
|
||||
#define BP_UARTDBGIMSC_RESERVED 11
|
||||
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGIMSC_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
|
||||
#define BM_UARTDBGIMSC_OEIM 0x00000400
|
||||
#define BM_UARTDBGIMSC_BEIM 0x00000200
|
||||
#define BM_UARTDBGIMSC_PEIM 0x00000100
|
||||
#define BM_UARTDBGIMSC_FEIM 0x00000080
|
||||
#define BM_UARTDBGIMSC_RTIM 0x00000040
|
||||
#define BM_UARTDBGIMSC_TXIM 0x00000020
|
||||
#define BM_UARTDBGIMSC_RXIM 0x00000010
|
||||
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
|
||||
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
|
||||
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
|
||||
#define BM_UARTDBGIMSC_RIMIM 0x00000001
|
||||
#define HW_UARTDBGRIS 0x0000003c
|
||||
#define BP_UARTDBGRIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGRIS_RESERVED 11
|
||||
#define BM_UARTDBGRIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGRIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
|
||||
#define BM_UARTDBGRIS_OERIS 0x00000400
|
||||
#define BM_UARTDBGRIS_BERIS 0x00000200
|
||||
#define BM_UARTDBGRIS_PERIS 0x00000100
|
||||
#define BM_UARTDBGRIS_FERIS 0x00000080
|
||||
#define BM_UARTDBGRIS_RTRIS 0x00000040
|
||||
#define BM_UARTDBGRIS_TXRIS 0x00000020
|
||||
#define BM_UARTDBGRIS_RXRIS 0x00000010
|
||||
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
|
||||
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
|
||||
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
|
||||
#define BM_UARTDBGRIS_RIRMIS 0x00000001
|
||||
#define HW_UARTDBGMIS 0x00000040
|
||||
#define BP_UARTDBGMIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGMIS_RESERVED 11
|
||||
#define BM_UARTDBGMIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGMIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
|
||||
#define BM_UARTDBGMIS_OEMIS 0x00000400
|
||||
#define BM_UARTDBGMIS_BEMIS 0x00000200
|
||||
#define BM_UARTDBGMIS_PEMIS 0x00000100
|
||||
#define BM_UARTDBGMIS_FEMIS 0x00000080
|
||||
#define BM_UARTDBGMIS_RTMIS 0x00000040
|
||||
#define BM_UARTDBGMIS_TXMIS 0x00000020
|
||||
#define BM_UARTDBGMIS_RXMIS 0x00000010
|
||||
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
|
||||
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
|
||||
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
|
||||
#define BM_UARTDBGMIS_RIMMIS 0x00000001
|
||||
#define HW_UARTDBGICR 0x00000044
|
||||
#define BP_UARTDBGICR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGICR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
|
||||
#define BP_UARTDBGICR_RESERVED 11
|
||||
#define BM_UARTDBGICR_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGICR_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGICR_RESERVED)
|
||||
#define BM_UARTDBGICR_OEIC 0x00000400
|
||||
#define BM_UARTDBGICR_BEIC 0x00000200
|
||||
#define BM_UARTDBGICR_PEIC 0x00000100
|
||||
#define BM_UARTDBGICR_FEIC 0x00000080
|
||||
#define BM_UARTDBGICR_RTIC 0x00000040
|
||||
#define BM_UARTDBGICR_TXIC 0x00000020
|
||||
#define BM_UARTDBGICR_RXIC 0x00000010
|
||||
#define BM_UARTDBGICR_DSRMIC 0x00000008
|
||||
#define BM_UARTDBGICR_DCDMIC 0x00000004
|
||||
#define BM_UARTDBGICR_CTSMIC 0x00000002
|
||||
#define BM_UARTDBGICR_RIMIC 0x00000001
|
||||
#define HW_UARTDBGDMACR 0x00000048
|
||||
#define BP_UARTDBGDMACR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDMACR_RESERVED 3
|
||||
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
|
||||
#define BF_UARTDBGDMACR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
|
||||
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
|
||||
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
|
||||
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* stmp378x: USBCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
|
||||
#define REGS_USBCTRL_PHYS 0x80080000
|
||||
#define REGS_USBCTRL_SIZE 0x2000
|
||||
|
||||
#define HW_USBCTRL_USBCMD 0x140
|
||||
#define BM_USBCTRL_USBCMD_RS 0x00000001
|
||||
#define BP_USBCTRL_USBCMD_RS 0
|
||||
#define BM_USBCTRL_USBCMD_RST 0x00000002
|
||||
|
||||
#define HW_USBCTRL_USBINTR 0x148
|
||||
#define BM_USBCTRL_USBINTR_UE 0x00000001
|
||||
#define BP_USBCTRL_USBINTR_UE 0
|
||||
|
||||
#define HW_USBCTRL_PORTSC1 0x184
|
||||
#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
|
||||
|
||||
#define HW_USBCTRL_OTGSC 0x1A4
|
||||
#define BM_USBCTRL_OTGSC_ID 0x00000100
|
||||
#define BM_USBCTRL_OTGSC_IDIS 0x00010000
|
||||
#define BM_USBCTRL_OTGSC_IDIE 0x01000000
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* stmp378x: USBPHY register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
|
||||
#define REGS_USBPHY_PHYS 0x8007C000
|
||||
#define REGS_USBPHY_SIZE 0x2000
|
||||
|
||||
#define HW_USBPHY_PWD 0x0
|
||||
|
||||
#define HW_USBPHY_CTRL 0x30
|
||||
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
|
||||
#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
|
||||
#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
|
||||
#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
|
||||
#define BM_USBPHY_CTRL_CLKGATE 0x40000000
|
||||
#define BM_USBPHY_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_USBPHY_STATUS 0x40
|
||||
#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
|
||||
#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
/*
|
||||
* Freescale STMP378X platform support
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <asm/dma.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/pins.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/system.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/regs-icoll.h>
|
||||
#include <mach/regs-apbh.h>
|
||||
#include <mach/regs-apbx.h>
|
||||
#include <mach/regs-pxp.h>
|
||||
#include <mach/regs-i2c.h>
|
||||
|
||||
#include "stmp378x.h"
|
||||
/*
|
||||
* IRQ handling
|
||||
*/
|
||||
static void stmp378x_ack_irq(unsigned int irq)
|
||||
{
|
||||
/* Tell ICOLL to release IRQ line */
|
||||
__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
|
||||
|
||||
/* ACK current interrupt */
|
||||
__raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
|
||||
REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
|
||||
|
||||
/* Barrier */
|
||||
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
|
||||
}
|
||||
|
||||
static void stmp378x_mask_irq(unsigned int irq)
|
||||
{
|
||||
/* IRQ disable */
|
||||
stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
|
||||
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
|
||||
}
|
||||
|
||||
static void stmp378x_unmask_irq(unsigned int irq)
|
||||
{
|
||||
/* IRQ enable */
|
||||
stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
|
||||
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
|
||||
}
|
||||
|
||||
static struct irq_chip stmp378x_chip = {
|
||||
.ack = stmp378x_ack_irq,
|
||||
.mask = stmp378x_mask_irq,
|
||||
.unmask = stmp378x_unmask_irq,
|
||||
};
|
||||
|
||||
void __init stmp378x_init_irq(void)
|
||||
{
|
||||
stmp3xxx_init_irq(&stmp378x_chip);
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA interrupt handling
|
||||
*/
|
||||
void stmp3xxx_arch_dma_enable_interrupt(int channel)
|
||||
{
|
||||
void __iomem *c1, *c2;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
|
||||
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
|
||||
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
|
||||
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
|
||||
|
||||
void stmp3xxx_arch_dma_clear_interrupt(int channel)
|
||||
{
|
||||
void __iomem *c1, *c2;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
|
||||
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
|
||||
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
|
||||
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
|
||||
|
||||
int stmp3xxx_arch_dma_is_interrupt(int channel)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
|
||||
(1 << STMP3XXX_DMA_CHANNEL(channel));
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
|
||||
(1 << STMP3XXX_DMA_CHANNEL(channel));
|
||||
break;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
|
||||
|
||||
void stmp3xxx_arch_dma_reset_channel(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
void __iomem *c0;
|
||||
u32 mask;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
|
||||
mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
|
||||
mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset channel and wait for it to complete */
|
||||
stmp3xxx_setl(mask, c0);
|
||||
while (__raw_readl(c0) & mask)
|
||||
cpu_relax();
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
|
||||
|
||||
void stmp3xxx_arch_dma_freeze(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
u32 mask = 1 << chbit;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
|
||||
|
||||
void stmp3xxx_arch_dma_unfreeze(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
u32 mask = 1 << chbit;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
|
||||
|
||||
/*
|
||||
* The registers are all very closely mapped, so we might as well map them all
|
||||
* with a single mapping
|
||||
*
|
||||
* Logical Physical
|
||||
* f0000000 80000000 On-chip registers
|
||||
* f1000000 00000000 32k on-chip SRAM
|
||||
*/
|
||||
|
||||
static struct map_desc stmp378x_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (u32)STMP3XXX_REGS_BASE,
|
||||
.pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
|
||||
.length = STMP3XXX_REGS_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = (u32)STMP3XXX_OCRAM_BASE,
|
||||
.pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
|
||||
.length = STMP3XXX_OCRAM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static u64 common_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
/*
|
||||
* devices that are present only on stmp378x, not on all 3xxx boards:
|
||||
* PxP
|
||||
* I2C
|
||||
*/
|
||||
static struct resource pxp_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = REGS_PXP_PHYS,
|
||||
.end = REGS_PXP_PHYS + REGS_PXP_SIZE,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_PXP,
|
||||
.end = IRQ_PXP,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp378x_pxp = {
|
||||
.name = "stmp3xxx-pxp",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(pxp_resource),
|
||||
.resource = pxp_resource,
|
||||
};
|
||||
|
||||
static struct resource i2c_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_I2C_ERROR,
|
||||
.end = IRQ_I2C_ERROR,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = REGS_I2C_PHYS,
|
||||
.end = REGS_I2C_PHYS + REGS_I2C_SIZE,
|
||||
}, {
|
||||
.flags = IORESOURCE_DMA,
|
||||
.start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
|
||||
.end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp378x_i2c = {
|
||||
.name = "i2c_stmp3xxx",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = i2c_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c_resources),
|
||||
};
|
||||
|
||||
void __init stmp378x_map_io(void)
|
||||
{
|
||||
iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X internal functions and data declarations
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __MACH_STMP378X_H
|
||||
#define __MACH_STMP378X_H
|
||||
|
||||
void stmp378x_map_io(void);
|
||||
void stmp378x_init_irq(void);
|
||||
|
||||
extern struct platform_device stmp378x_pxp, stmp378x_i2c;
|
||||
#endif /* __MACH_STMP378X_COMMON_H */
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/*
|
||||
* Freescale STMP378X development board support
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include <mach/pins.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/mmc.h>
|
||||
#include <mach/gpmi.h>
|
||||
|
||||
#include "stmp378x.h"
|
||||
|
||||
static struct platform_device *devices[] = {
|
||||
&stmp3xxx_dbguart,
|
||||
&stmp3xxx_appuart,
|
||||
&stmp3xxx_watchdog,
|
||||
&stmp3xxx_touchscreen,
|
||||
&stmp3xxx_rtc,
|
||||
&stmp3xxx_keyboard,
|
||||
&stmp3xxx_framebuffer,
|
||||
&stmp3xxx_backlight,
|
||||
&stmp3xxx_rotdec,
|
||||
&stmp3xxx_persistent,
|
||||
&stmp3xxx_dcp_bootstream,
|
||||
&stmp3xxx_dcp,
|
||||
&stmp3xxx_battery,
|
||||
&stmp378x_pxp,
|
||||
&stmp378x_i2c,
|
||||
};
|
||||
|
||||
static struct pin_desc i2c_pins_desc[] = {
|
||||
{ PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
};
|
||||
|
||||
static struct pin_group i2c_pins = {
|
||||
.pins = i2c_pins_desc,
|
||||
.nr_pins = ARRAY_SIZE(i2c_pins_desc),
|
||||
};
|
||||
|
||||
static struct pin_desc dbguart_pins_0[] = {
|
||||
{ PINID_PWM0, PIN_FUN3, },
|
||||
{ PINID_PWM1, PIN_FUN3, },
|
||||
};
|
||||
|
||||
static struct pin_group dbguart_pins[] = {
|
||||
[0] = {
|
||||
.pins = dbguart_pins_0,
|
||||
.nr_pins = ARRAY_SIZE(dbguart_pins_0),
|
||||
},
|
||||
};
|
||||
|
||||
static int dbguart_pins_control(int id, int request)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
if (request)
|
||||
r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
|
||||
else
|
||||
stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct pin_desc appuart_pins_0[] = {
|
||||
{ PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
};
|
||||
|
||||
static struct pin_desc appuart_pins_1[] = {
|
||||
#if 0 /* enable these when second appuart will be connected */
|
||||
{ PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct pin_desc mmc_pins_desc[] = {
|
||||
{ PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
|
||||
{ PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
|
||||
{ PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
|
||||
{ PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
|
||||
{ PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
|
||||
{ PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
|
||||
{ PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
|
||||
};
|
||||
|
||||
static struct pin_group mmc_pins = {
|
||||
.pins = mmc_pins_desc,
|
||||
.nr_pins = ARRAY_SIZE(mmc_pins_desc),
|
||||
};
|
||||
|
||||
static int stmp3xxxmmc_get_wp(void)
|
||||
{
|
||||
return gpio_get_value(PINID_PWM4);
|
||||
}
|
||||
|
||||
static int stmp3xxxmmc_hw_init_ssp1(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Configure write protect GPIO pin */
|
||||
ret = gpio_request(PINID_PWM4, "mmc wp");
|
||||
if (ret)
|
||||
goto out_wp;
|
||||
|
||||
gpio_direction_input(PINID_PWM4);
|
||||
|
||||
/* Configure POWER pin as gpio to drive power to MMC slot */
|
||||
ret = gpio_request(PINID_PWM3, "mmc power");
|
||||
if (ret)
|
||||
goto out_power;
|
||||
|
||||
gpio_direction_output(PINID_PWM3, 0);
|
||||
mdelay(100);
|
||||
|
||||
return 0;
|
||||
|
||||
out_power:
|
||||
gpio_free(PINID_PWM4);
|
||||
out_wp:
|
||||
stmp3xxx_release_pin_group(&mmc_pins, "mmc");
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void stmp3xxxmmc_hw_release_ssp1(void)
|
||||
{
|
||||
gpio_free(PINID_PWM3);
|
||||
gpio_free(PINID_PWM4);
|
||||
stmp3xxx_release_pin_group(&mmc_pins, "mmc");
|
||||
}
|
||||
|
||||
static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
|
||||
{
|
||||
stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
|
||||
{
|
||||
struct clk *ssp, *parent;
|
||||
char *p;
|
||||
long r;
|
||||
|
||||
ssp = clk_get(NULL, "ssp");
|
||||
|
||||
/* using SSP1, no timeout, clock rate 1 */
|
||||
writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
|
||||
BF(0xFFFF, SSP_TIMING_TIMEOUT),
|
||||
base + HW_SSP_TIMING);
|
||||
|
||||
p = (hz > 1000000) ? "io" : "osc_24M";
|
||||
parent = clk_get(NULL, p);
|
||||
clk_set_parent(ssp, parent);
|
||||
r = clk_set_rate(ssp, 2 * hz / 1000);
|
||||
clk_put(parent);
|
||||
clk_put(ssp);
|
||||
|
||||
return hz;
|
||||
}
|
||||
|
||||
static struct stmp3xxxmmc_platform_data mmc_data = {
|
||||
.hw_init = stmp3xxxmmc_hw_init_ssp1,
|
||||
.hw_release = stmp3xxxmmc_hw_release_ssp1,
|
||||
.get_wp = stmp3xxxmmc_get_wp,
|
||||
.cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
|
||||
.setclock = stmp3xxxmmc_setclock_ssp1,
|
||||
};
|
||||
|
||||
|
||||
static struct pin_group appuart_pins[] = {
|
||||
[0] = {
|
||||
.pins = appuart_pins_0,
|
||||
.nr_pins = ARRAY_SIZE(appuart_pins_0),
|
||||
},
|
||||
[1] = {
|
||||
.pins = appuart_pins_1,
|
||||
.nr_pins = ARRAY_SIZE(appuart_pins_1),
|
||||
},
|
||||
};
|
||||
|
||||
static struct pin_desc ssp1_pins_desc[] = {
|
||||
{ PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
|
||||
{ PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
|
||||
{ PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
|
||||
{ PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
|
||||
};
|
||||
|
||||
static struct pin_desc ssp2_pins_desc[] = {
|
||||
{ PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
|
||||
{ PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
|
||||
{ PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
|
||||
{ PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
|
||||
};
|
||||
|
||||
static struct pin_group ssp1_pins = {
|
||||
.pins = ssp1_pins_desc,
|
||||
.nr_pins = ARRAY_SIZE(ssp1_pins_desc),
|
||||
};
|
||||
|
||||
static struct pin_group ssp2_pins = {
|
||||
.pins = ssp1_pins_desc,
|
||||
.nr_pins = ARRAY_SIZE(ssp2_pins_desc),
|
||||
};
|
||||
|
||||
static struct pin_desc gpmi_pins_desc[] = {
|
||||
{ PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
|
||||
{ PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
|
||||
};
|
||||
|
||||
static struct pin_group gpmi_pins = {
|
||||
.pins = gpmi_pins_desc,
|
||||
.nr_pins = ARRAY_SIZE(gpmi_pins_desc),
|
||||
};
|
||||
|
||||
static struct mtd_partition gpmi_partitions[] = {
|
||||
[0] = {
|
||||
.name = "boot",
|
||||
.size = 10 * SZ_1M,
|
||||
.offset = 0,
|
||||
},
|
||||
[1] = {
|
||||
.name = "data",
|
||||
.size = MTDPART_SIZ_FULL,
|
||||
.offset = MTDPART_OFS_APPEND,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpmi_platform_data gpmi_data = {
|
||||
.pins = &gpmi_pins,
|
||||
.nr_parts = ARRAY_SIZE(gpmi_partitions),
|
||||
.parts = gpmi_partitions,
|
||||
.part_types = { "cmdline", NULL },
|
||||
};
|
||||
|
||||
static struct spi_board_info spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
|
||||
{
|
||||
.modalias = "enc28j60",
|
||||
.max_speed_hz = 6 * 1000 * 1000,
|
||||
.bus_num = 1,
|
||||
.chip_select = 0,
|
||||
.platform_data = NULL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static void __init stmp378x_devb_init(void)
|
||||
{
|
||||
stmp3xxx_pinmux_init(NR_REAL_IRQS);
|
||||
|
||||
/* init stmp3xxx platform */
|
||||
stmp3xxx_init();
|
||||
|
||||
stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
|
||||
stmp3xxx_appuart.dev.platform_data = appuart_pins;
|
||||
stmp3xxx_mmc.dev.platform_data = &mmc_data;
|
||||
stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
|
||||
stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
|
||||
stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
|
||||
stmp378x_i2c.dev.platform_data = &i2c_pins;
|
||||
|
||||
/* register spi devices */
|
||||
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
||||
|
||||
/* add board's devices */
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
||||
/* add devices selected by command line ssp1= and ssp2= options */
|
||||
stmp3xxx_ssp1_device_register();
|
||||
stmp3xxx_ssp2_device_register();
|
||||
}
|
||||
|
||||
MACHINE_START(STMP378X, "STMP378X")
|
||||
.phys_io = 0x80000000,
|
||||
.io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x40000100,
|
||||
.map_io = stmp378x_map_io,
|
||||
.init_irq = stmp378x_init_irq,
|
||||
.timer = &stmp3xxx_timer,
|
||||
.init_machine = stmp378x_devb_init,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
|
||||
obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
zreladdr-y := 0x40008000
|
||||
params_phys-y := 0x40000100
|
||||
initrd_phys-y := 0x40800000
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* Low-level IRQ helper macros for Freescale STMP37XX
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
|
||||
mov \base, #0xf0000000 @ vm address of IRQ controller
|
||||
ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
|
||||
cmp \irqnr, #0x3f
|
||||
movne \irqstat, #0 @ Ack this IRQ
|
||||
strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
|
||||
moveqs \irqnr, #0 @ Zero flag set for no IRQ
|
||||
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
.endm
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Freescale STMP37XX interrupts
|
||||
*
|
||||
* Copyright (C) 2005 Sigmatel Inc
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef _ASM_ARCH_IRQS_H
|
||||
#define _ASM_ARCH_IRQS_H
|
||||
|
||||
#define IRQ_DEBUG_UART 0
|
||||
#define IRQ_COMMS_RX 1
|
||||
#define IRQ_COMMS_TX 1
|
||||
#define IRQ_SSP2_ERROR 2
|
||||
#define IRQ_VDD5V 3
|
||||
#define IRQ_HEADPHONE_SHORT 4
|
||||
#define IRQ_DAC_DMA 5
|
||||
#define IRQ_DAC_ERROR 6
|
||||
#define IRQ_ADC_DMA 7
|
||||
#define IRQ_ADC_ERROR 8
|
||||
#define IRQ_SPDIF_DMA 9
|
||||
#define IRQ_SAIF2_DMA 9
|
||||
#define IRQ_SPDIF_ERROR 10
|
||||
#define IRQ_SAIF1_IRQ 10
|
||||
#define IRQ_SAIF2_IRQ 10
|
||||
#define IRQ_USB_CTRL 11
|
||||
#define IRQ_USB_WAKEUP 12
|
||||
#define IRQ_GPMI_DMA 13
|
||||
#define IRQ_SSP1_DMA 14
|
||||
#define IRQ_SSP_ERROR 15
|
||||
#define IRQ_GPIO0 16
|
||||
#define IRQ_GPIO1 17
|
||||
#define IRQ_GPIO2 18
|
||||
#define IRQ_SAIF1_DMA 19
|
||||
#define IRQ_SSP2_DMA 20
|
||||
#define IRQ_ECC8_IRQ 21
|
||||
#define IRQ_RTC_ALARM 22
|
||||
#define IRQ_UARTAPP_TX_DMA 23
|
||||
#define IRQ_UARTAPP_INTERNAL 24
|
||||
#define IRQ_UARTAPP_RX_DMA 25
|
||||
#define IRQ_I2C_DMA 26
|
||||
#define IRQ_I2C_ERROR 27
|
||||
#define IRQ_TIMER0 28
|
||||
#define IRQ_TIMER1 29
|
||||
#define IRQ_TIMER2 30
|
||||
#define IRQ_TIMER3 31
|
||||
#define IRQ_BATT_BRNOUT 32
|
||||
#define IRQ_VDDD_BRNOUT 33
|
||||
#define IRQ_VDDIO_BRNOUT 34
|
||||
#define IRQ_VDD18_BRNOUT 35
|
||||
#define IRQ_TOUCH_DETECT 36
|
||||
#define IRQ_LRADC_CH0 37
|
||||
#define IRQ_LRADC_CH1 38
|
||||
#define IRQ_LRADC_CH2 39
|
||||
#define IRQ_LRADC_CH3 40
|
||||
#define IRQ_LRADC_CH4 41
|
||||
#define IRQ_LRADC_CH5 42
|
||||
#define IRQ_LRADC_CH6 43
|
||||
#define IRQ_LRADC_CH7 44
|
||||
#define IRQ_LCDIF_DMA 45
|
||||
#define IRQ_LCDIF_ERROR 46
|
||||
#define IRQ_DIGCTL_DEBUG_TRAP 47
|
||||
#define IRQ_RTC_1MSEC 48
|
||||
#define IRQ_DRI_DMA 49
|
||||
#define IRQ_DRI_ATTENTION 50
|
||||
#define IRQ_GPMI_ATTENTION 51
|
||||
#define IRQ_IR 52
|
||||
#define IRQ_DCP_VMI 53
|
||||
#define IRQ_DCP 54
|
||||
#define IRQ_RESERVED_55 55
|
||||
#define IRQ_RESERVED_56 56
|
||||
#define IRQ_RESERVED_57 57
|
||||
#define IRQ_RESERVED_58 58
|
||||
#define IRQ_RESERVED_59 59
|
||||
#define SW_IRQ_60 60
|
||||
#define SW_IRQ_61 61
|
||||
#define SW_IRQ_62 62
|
||||
#define SW_IRQ_63 63
|
||||
|
||||
#define NR_REAL_IRQS 64
|
||||
#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
|
||||
|
||||
/* TIMER and BRNOUT are FIQ capable */
|
||||
#define FIQ_START IRQ_TIMER0
|
||||
|
||||
/* Hard disk IRQ is a GPMI attention IRQ */
|
||||
#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
|
||||
|
||||
#endif /* _ASM_ARCH_IRQS_H */
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Freescale STMP37XX SoC pin multiplexing
|
||||
*
|
||||
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_ARCH_PINS_H
|
||||
#define __ASM_ARCH_PINS_H
|
||||
|
||||
/*
|
||||
* Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
|
||||
* interface this pin belongs to.
|
||||
*/
|
||||
|
||||
/* Bank 0 */
|
||||
#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
|
||||
#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
|
||||
#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
|
||||
#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
|
||||
#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
|
||||
#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
|
||||
#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
|
||||
#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
|
||||
#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
|
||||
#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
|
||||
#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
|
||||
#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
|
||||
#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
|
||||
#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
|
||||
#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
|
||||
#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
|
||||
#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
|
||||
#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
|
||||
#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
|
||||
#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
|
||||
#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
|
||||
#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
|
||||
#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
|
||||
#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
|
||||
#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
|
||||
#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
|
||||
#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
|
||||
#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
|
||||
#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
|
||||
#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
|
||||
|
||||
/* Bank 1 */
|
||||
#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
|
||||
#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
|
||||
#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
|
||||
#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
|
||||
#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
|
||||
#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
|
||||
#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
|
||||
#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
|
||||
#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
|
||||
#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
|
||||
#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
|
||||
#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
|
||||
#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
|
||||
#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
|
||||
#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
|
||||
#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
|
||||
#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
|
||||
#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
|
||||
#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
|
||||
#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
|
||||
#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
|
||||
#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
|
||||
#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
|
||||
#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
|
||||
#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
|
||||
#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
|
||||
#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
|
||||
#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
|
||||
#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
|
||||
|
||||
/* Bank 2 */
|
||||
#define PINID_PWM0 STMP3XXX_PINID(2, 0)
|
||||
#define PINID_PWM1 STMP3XXX_PINID(2, 1)
|
||||
#define PINID_PWM2 STMP3XXX_PINID(2, 2)
|
||||
#define PINID_PWM3 STMP3XXX_PINID(2, 3)
|
||||
#define PINID_PWM4 STMP3XXX_PINID(2, 4)
|
||||
#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
|
||||
#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
|
||||
#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
|
||||
#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
|
||||
#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
|
||||
#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
|
||||
#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
|
||||
#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
|
||||
#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
|
||||
#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
|
||||
#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
|
||||
#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
|
||||
#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
|
||||
#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
|
||||
#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
|
||||
#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
|
||||
#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
|
||||
#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
|
||||
#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
|
||||
#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
|
||||
#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
|
||||
#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
|
||||
#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
|
||||
#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
|
||||
#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
|
||||
#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
|
||||
#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
|
||||
|
||||
/* Bank 3 */
|
||||
#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
|
||||
#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
|
||||
#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
|
||||
#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
|
||||
#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
|
||||
#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
|
||||
#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
|
||||
#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
|
||||
#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
|
||||
#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
|
||||
#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
|
||||
#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
|
||||
#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
|
||||
#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
|
||||
#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
|
||||
#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
|
||||
#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
|
||||
#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
|
||||
#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
|
||||
#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
|
||||
#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
|
||||
#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
|
||||
|
||||
#endif /* __ASM_ARCH_PINS_H */
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* stmp37xx: APBH register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_APBH
|
||||
#define _MACH_REGS_APBH
|
||||
|
||||
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
|
||||
|
||||
#define HW_APBH_CTRL0 0x0
|
||||
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
|
||||
#define BP_APBH_CTRL0_RESET_CHANNEL 16
|
||||
#define BM_APBH_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBH_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_APBH_CTRL1 0x10
|
||||
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
|
||||
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
|
||||
|
||||
#define HW_APBH_DEVSEL 0x20
|
||||
|
||||
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_NXTCMDAR 0x50
|
||||
|
||||
#define BM_APBH_CHn_CMD_MODE 0x00000003
|
||||
#define BP_APBH_CHn_CMD_MODE 0x00000001
|
||||
#define BV_APBH_CHn_CMD_MODE_NOOP 0
|
||||
#define BV_APBH_CHn_CMD_MODE_WRITE 1
|
||||
#define BV_APBH_CHn_CMD_MODE_READ 2
|
||||
#define BV_APBH_CHn_CMD_MODE_SENSE 3
|
||||
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
|
||||
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
|
||||
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBH_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBH_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
|
||||
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
|
||||
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
|
||||
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
|
||||
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
|
||||
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
|
||||
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
|
||||
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
|
||||
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
|
||||
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
|
||||
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
|
||||
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
|
||||
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
|
||||
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
|
||||
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
|
||||
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
|
||||
|
||||
#define HW_APBH_CHn_SEMA 0x80
|
||||
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBH_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* stmp37xx: APBX register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_APBX
|
||||
#define _MACH_REGS_APBX
|
||||
|
||||
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
|
||||
|
||||
#define HW_APBX_CTRL0 0x0
|
||||
#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
|
||||
#define BP_APBX_CTRL0_RESET_CHANNEL 16
|
||||
#define BM_APBX_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_APBX_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_APBX_CTRL1 0x10
|
||||
|
||||
#define HW_APBX_DEVSEL 0x20
|
||||
|
||||
#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_NXTCMDAR 0x50
|
||||
#define BM_APBX_CHn_CMD_MODE 0x00000003
|
||||
#define BP_APBX_CHn_CMD_MODE 0x00000001
|
||||
#define BV_APBX_CHn_CMD_MODE_NOOP 0
|
||||
#define BV_APBX_CHn_CMD_MODE_WRITE 1
|
||||
#define BV_APBX_CHn_CMD_MODE_READ 2
|
||||
#define BV_APBX_CHn_CMD_MODE_SENSE 3
|
||||
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
|
||||
#define BP_APBX_CHn_CMD_COMMAND 0
|
||||
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
|
||||
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
|
||||
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
|
||||
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
|
||||
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
|
||||
#define BP_APBX_CHn_CMD_CMDWORDS 12
|
||||
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
|
||||
#define BP_APBX_CHn_CMD_XFER_COUNT 16
|
||||
|
||||
#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_BAR 0x70
|
||||
|
||||
#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
|
||||
#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
|
||||
#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
|
||||
#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
|
||||
#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
|
||||
#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
|
||||
#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
|
||||
#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
|
||||
#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
|
||||
#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
|
||||
#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
|
||||
#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
|
||||
#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
|
||||
#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
|
||||
#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
|
||||
#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
|
||||
|
||||
#define HW_APBX_CHn_SEMA 0x80
|
||||
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
|
||||
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
|
||||
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
|
||||
#define BP_APBX_CHn_SEMA_PHORE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* stmp37xx: AUDIOIN register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
|
||||
|
||||
#define HW_AUDIOIN_CTRL 0x0
|
||||
#define BM_AUDIOIN_CTRL_RUN 0x00000001
|
||||
#define BP_AUDIOIN_CTRL_RUN 0
|
||||
#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
|
||||
#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
|
||||
#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_AUDIOIN_STAT 0x10
|
||||
|
||||
#define HW_AUDIOIN_ADCSRR 0x20
|
||||
|
||||
#define HW_AUDIOIN_ADCVOLUME 0x30
|
||||
#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
|
||||
#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
|
||||
#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
|
||||
#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
|
||||
|
||||
#define HW_AUDIOIN_ADCDEBUG 0x40
|
||||
|
||||
#define HW_AUDIOIN_ADCVOL 0x50
|
||||
#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
|
||||
#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
|
||||
#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
|
||||
#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
|
||||
#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
|
||||
#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
|
||||
#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
|
||||
#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
|
||||
#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
|
||||
|
||||
#define HW_AUDIOIN_MICLINE 0x60
|
||||
|
||||
#define HW_AUDIOIN_ANACLKCTRL 0x70
|
||||
#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
|
||||
|
||||
#define HW_AUDIOIN_DATA 0x80
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/*
|
||||
* stmp37xx: AUDIOOUT register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
|
||||
|
||||
#define HW_AUDIOOUT_CTRL 0x0
|
||||
#define BM_AUDIOOUT_CTRL_RUN 0x00000001
|
||||
#define BP_AUDIOOUT_CTRL_RUN 0
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
|
||||
#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
|
||||
#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
|
||||
#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
|
||||
#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_AUDIOOUT_STAT 0x10
|
||||
|
||||
#define HW_AUDIOOUT_DACSRR 0x20
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_INT 16
|
||||
#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
|
||||
#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
|
||||
#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
|
||||
#define BP_AUDIOOUT_DACSRR_BASEMULT 28
|
||||
|
||||
#define HW_AUDIOOUT_DACVOLUME 0x30
|
||||
#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
|
||||
#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
|
||||
#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_DACDEBUG 0x40
|
||||
|
||||
#define HW_AUDIOOUT_HPVOL 0x50
|
||||
#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
|
||||
#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_PWRDN 0x70
|
||||
#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
|
||||
#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
|
||||
#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
|
||||
#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
|
||||
#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
|
||||
#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
|
||||
#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
|
||||
|
||||
#define HW_AUDIOOUT_REFCTRL 0x80
|
||||
#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
|
||||
#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
|
||||
#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
|
||||
#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
|
||||
#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
|
||||
#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
|
||||
#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
|
||||
#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
|
||||
#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
|
||||
#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
|
||||
#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
|
||||
#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
|
||||
#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_ANACTRL 0x90
|
||||
#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
|
||||
#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
|
||||
|
||||
#define HW_AUDIOOUT_TEST 0xA0
|
||||
#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
|
||||
#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
|
||||
|
||||
#define HW_AUDIOOUT_BISTCTRL 0xB0
|
||||
|
||||
#define HW_AUDIOOUT_BISTSTAT0 0xC0
|
||||
|
||||
#define HW_AUDIOOUT_BISTSTAT1 0xD0
|
||||
|
||||
#define HW_AUDIOOUT_ANACLKCTRL 0xE0
|
||||
#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
|
||||
|
||||
#define HW_AUDIOOUT_DATA 0xF0
|
||||
|
||||
#define HW_AUDIOOUT_LINEOUTCTRL 0x100
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
|
||||
#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
|
||||
#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
|
||||
#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
|
||||
#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
|
||||
#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
|
||||
|
||||
#define HW_AUDIOOUT_VERSION 0x200
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* stmp37xx: CLKCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_CLKCTRL
|
||||
#define _MACH_REGS_CLKCTRL
|
||||
|
||||
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
|
||||
|
||||
#define HW_CLKCTRL_PLLCTRL0 0x0
|
||||
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
|
||||
|
||||
#define HW_CLKCTRL_CPU 0x20
|
||||
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
|
||||
#define BP_CLKCTRL_CPU_DIV_CPU 0
|
||||
|
||||
#define HW_CLKCTRL_HBUS 0x30
|
||||
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
|
||||
#define BP_CLKCTRL_HBUS_DIV 0
|
||||
|
||||
#define HW_CLKCTRL_XBUS 0x40
|
||||
|
||||
#define HW_CLKCTRL_XTAL 0x50
|
||||
|
||||
#define HW_CLKCTRL_PIX 0x60
|
||||
#define BM_CLKCTRL_PIX_DIV 0x00007FFF
|
||||
#define BP_CLKCTRL_PIX_DIV 0
|
||||
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
|
||||
|
||||
#define HW_CLKCTRL_SSP 0x70
|
||||
|
||||
#define HW_CLKCTRL_GPMI 0x80
|
||||
|
||||
#define HW_CLKCTRL_SPDIF 0x90
|
||||
|
||||
#define HW_CLKCTRL_EMI 0xA0
|
||||
|
||||
#define HW_CLKCTRL_IR 0xB0
|
||||
|
||||
#define HW_CLKCTRL_SAIF 0xC0
|
||||
|
||||
#define HW_CLKCTRL_FRAC 0xD0
|
||||
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
|
||||
#define BP_CLKCTRL_FRAC_EMIFRAC 8
|
||||
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
|
||||
#define BP_CLKCTRL_FRAC_PIXFRAC 16
|
||||
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
|
||||
|
||||
#define HW_CLKCTRL_CLKSEQ 0xE0
|
||||
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
|
||||
|
||||
#define HW_CLKCTRL_RESET 0xF0
|
||||
#define BM_CLKCTRL_RESET_DIG 0x00000001
|
||||
#define BP_CLKCTRL_RESET_DIG 0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* stmp37xx: DIGCTL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
|
||||
|
||||
#define HW_DIGCTL_CTRL 0x0
|
||||
#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* stmp37xx: ECC8 register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
|
||||
|
||||
#define HW_ECC8_CTRL 0x0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
|
||||
#define BP_ECC8_CTRL_COMPLETE_IRQ 0
|
||||
#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
|
||||
#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
|
||||
|
||||
#define HW_ECC8_STATUS0 0x10
|
||||
#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
|
||||
#define BM_ECC8_STATUS0_CORRECTED 0x00000008
|
||||
#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
|
||||
#define BP_ECC8_STATUS0_STATUS_AUX 8
|
||||
#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
|
||||
#define BP_ECC8_STATUS0_COMPLETED_CE 16
|
||||
|
||||
#define HW_ECC8_STATUS1 0x20
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* stmp37xx: GPMI register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
|
||||
#define REGS_GPMI_PHYS 0x8000C000
|
||||
#define REGS_GPMI_SIZE 0x2000
|
||||
|
||||
#define HW_GPMI_CTRL0 0x0
|
||||
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_GPMI_CTRL0_XFER_COUNT 0
|
||||
#define BM_GPMI_CTRL0_CS 0x00300000
|
||||
#define BP_GPMI_CTRL0_CS 20
|
||||
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
|
||||
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
|
||||
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
|
||||
#define BP_GPMI_CTRL0_COMMAND_MODE 24
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
|
||||
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
|
||||
#define BM_GPMI_CTRL0_RUN 0x20000000
|
||||
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_GPMI_CTRL0_SFTRST 0x80000000
|
||||
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
|
||||
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
|
||||
#define BP_GPMI_ECCCTRL_ECC_CMD 13
|
||||
|
||||
#define HW_GPMI_CTRL1 0x60
|
||||
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
|
||||
#define BP_GPMI_CTRL1_GPMI_MODE 0
|
||||
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
|
||||
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
|
||||
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
|
||||
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
|
||||
#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
|
||||
#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
|
||||
|
||||
#define HW_GPMI_TIMING0 0x70
|
||||
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
|
||||
#define BP_GPMI_TIMING0_DATA_SETUP 0
|
||||
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
|
||||
#define BP_GPMI_TIMING0_DATA_HOLD 8
|
||||
|
||||
#define HW_GPMI_TIMING1 0x80
|
||||
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
|
||||
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* stmp37xx: I2C register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
|
||||
#define REGS_I2C_PHYS 0x80058000
|
||||
#define REGS_I2C_SIZE 0x2000
|
||||
|
||||
#define HW_I2C_CTRL0 0x0
|
||||
#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_I2C_CTRL0_XFER_COUNT 0
|
||||
#define BM_I2C_CTRL0_DIRECTION 0x00010000
|
||||
#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
|
||||
#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
|
||||
#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
|
||||
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
|
||||
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
|
||||
#define BM_I2C_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_I2C_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_I2C_TIMING0 0x10
|
||||
|
||||
#define HW_I2C_TIMING1 0x20
|
||||
|
||||
#define HW_I2C_TIMING2 0x30
|
||||
|
||||
#define HW_I2C_CTRL1 0x40
|
||||
#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
|
||||
#define BP_I2C_CTRL1_SLAVE_IRQ 0
|
||||
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
|
||||
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
|
||||
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
|
||||
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
|
||||
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
|
||||
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
|
||||
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
|
||||
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
|
||||
|
||||
#define HW_I2C_VERSION 0x90
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* stmp37xx: ICOLL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_ICOLL
|
||||
#define _MACH_REGS_ICOLL
|
||||
|
||||
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
|
||||
|
||||
#define HW_ICOLL_VECTOR 0x0
|
||||
|
||||
#define HW_ICOLL_LEVELACK 0x10
|
||||
|
||||
#define HW_ICOLL_CTRL 0x20
|
||||
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
|
||||
#define BM_ICOLL_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_ICOLL_STAT 0x30
|
||||
|
||||
#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
|
||||
#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
|
||||
#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
|
||||
#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
|
||||
|
||||
#define HW_ICOLL_PRIORITYn 0x60
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* stmp37xx: LCDIF register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
|
||||
#define REGS_LCDIF_PHYS 0x80030000
|
||||
#define REGS_LCDIF_SIZE 0x2000
|
||||
|
||||
#define HW_LCDIF_CTRL 0x0
|
||||
#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
|
||||
#define BP_LCDIF_CTRL_COUNT 0
|
||||
#define BM_LCDIF_CTRL_RUN 0x00010000
|
||||
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
|
||||
#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
|
||||
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
|
||||
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
|
||||
#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
|
||||
#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
|
||||
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
|
||||
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
|
||||
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
|
||||
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
|
||||
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
|
||||
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
|
||||
#define BM_LCDIF_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_LCDIF_CTRL1 0x10
|
||||
#define BM_LCDIF_CTRL1_RESET 0x00000001
|
||||
#define BP_LCDIF_CTRL1_RESET 0
|
||||
#define BM_LCDIF_CTRL1_MODE86 0x00000002
|
||||
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
|
||||
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
|
||||
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
|
||||
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
|
||||
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
|
||||
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
|
||||
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
|
||||
|
||||
#define HW_LCDIF_TIMING 0x20
|
||||
|
||||
#define HW_LCDIF_VDCTRL0 0x30
|
||||
#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
|
||||
#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
|
||||
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
|
||||
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
|
||||
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
|
||||
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
|
||||
|
||||
#define HW_LCDIF_VDCTRL1 0x40
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
|
||||
#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
|
||||
#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
|
||||
|
||||
#define HW_LCDIF_VDCTRL2 0x50
|
||||
#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
|
||||
#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
|
||||
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
|
||||
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
|
||||
|
||||
#define HW_LCDIF_VDCTRL3 0x60
|
||||
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
|
||||
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
|
||||
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
|
||||
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
|
||||
#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* stmp37xx: LRADC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
|
||||
|
||||
#define HW_LRADC_CTRL0 0x0
|
||||
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
|
||||
#define BP_LRADC_CTRL0_SCHEDULE 0
|
||||
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
|
||||
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
|
||||
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
|
||||
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
|
||||
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
|
||||
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
|
||||
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_LRADC_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_LRADC_CTRL1 0x10
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
|
||||
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
|
||||
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
|
||||
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
|
||||
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
|
||||
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
|
||||
|
||||
#define HW_LRADC_CTRL2 0x20
|
||||
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
|
||||
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
|
||||
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
|
||||
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
|
||||
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
|
||||
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
|
||||
|
||||
#define HW_LRADC_CTRL3 0x30
|
||||
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
|
||||
#define BP_LRADC_CTRL3_CYCLE_TIME 8
|
||||
|
||||
#define HW_LRADC_STATUS 0x40
|
||||
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
|
||||
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
|
||||
|
||||
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
|
||||
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
|
||||
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
|
||||
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
|
||||
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
|
||||
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
|
||||
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
|
||||
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
|
||||
|
||||
#define HW_LRADC_CHn 0x50
|
||||
#define BM_LRADC_CHn_VALUE 0x0003FFFF
|
||||
#define BP_LRADC_CHn_VALUE 0
|
||||
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
|
||||
#define BP_LRADC_CHn_NUM_SAMPLES 24
|
||||
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
|
||||
|
||||
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
|
||||
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
|
||||
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
|
||||
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
|
||||
|
||||
#define HW_LRADC_DELAYn 0xD0
|
||||
#define BM_LRADC_DELAYn_DELAY 0x000007FF
|
||||
#define BP_LRADC_DELAYn_DELAY 0
|
||||
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
|
||||
#define BP_LRADC_DELAYn_LOOP_COUNT 11
|
||||
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
|
||||
#define BM_LRADC_DELAYn_KICK 0x00100000
|
||||
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
|
||||
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
|
||||
|
||||
#define HW_LRADC_CTRL4 0x140
|
||||
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
|
||||
#define BP_LRADC_CTRL4_LRADC6SELECT 24
|
||||
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
|
||||
#define BP_LRADC_CTRL4_LRADC7SELECT 28
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* stmp37xx: PINCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_PINCTRL
|
||||
#define _MACH_REGS_PINCTRL
|
||||
|
||||
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
|
||||
|
||||
#define HW_PINCTRL_MUXSEL0 0x100
|
||||
#define HW_PINCTRL_MUXSEL1 0x110
|
||||
#define HW_PINCTRL_MUXSEL2 0x120
|
||||
#define HW_PINCTRL_MUXSEL3 0x130
|
||||
#define HW_PINCTRL_MUXSEL4 0x140
|
||||
#define HW_PINCTRL_MUXSEL5 0x150
|
||||
#define HW_PINCTRL_MUXSEL6 0x160
|
||||
#define HW_PINCTRL_MUXSEL7 0x170
|
||||
|
||||
#define HW_PINCTRL_DRIVE0 0x200
|
||||
#define HW_PINCTRL_DRIVE1 0x210
|
||||
#define HW_PINCTRL_DRIVE2 0x220
|
||||
#define HW_PINCTRL_DRIVE3 0x230
|
||||
#define HW_PINCTRL_DRIVE4 0x240
|
||||
#define HW_PINCTRL_DRIVE5 0x250
|
||||
#define HW_PINCTRL_DRIVE6 0x260
|
||||
#define HW_PINCTRL_DRIVE7 0x270
|
||||
#define HW_PINCTRL_DRIVE8 0x280
|
||||
#define HW_PINCTRL_DRIVE9 0x290
|
||||
#define HW_PINCTRL_DRIVE10 0x2A0
|
||||
#define HW_PINCTRL_DRIVE11 0x2B0
|
||||
#define HW_PINCTRL_DRIVE12 0x2C0
|
||||
#define HW_PINCTRL_DRIVE13 0x2D0
|
||||
#define HW_PINCTRL_DRIVE14 0x2E0
|
||||
|
||||
#define HW_PINCTRL_PULL0 0x300
|
||||
#define HW_PINCTRL_PULL1 0x310
|
||||
#define HW_PINCTRL_PULL2 0x320
|
||||
#define HW_PINCTRL_PULL3 0x330
|
||||
|
||||
#define HW_PINCTRL_DOUT0 0x400
|
||||
#define HW_PINCTRL_DOUT1 0x410
|
||||
#define HW_PINCTRL_DOUT2 0x420
|
||||
|
||||
#define HW_PINCTRL_DIN0 0x500
|
||||
#define HW_PINCTRL_DIN1 0x510
|
||||
#define HW_PINCTRL_DIN2 0x520
|
||||
|
||||
#define HW_PINCTRL_DOE0 0x600
|
||||
#define HW_PINCTRL_DOE1 0x610
|
||||
#define HW_PINCTRL_DOE2 0x620
|
||||
|
||||
#define HW_PINCTRL_PIN2IRQ0 0x700
|
||||
#define HW_PINCTRL_PIN2IRQ1 0x710
|
||||
#define HW_PINCTRL_PIN2IRQ2 0x720
|
||||
|
||||
#define HW_PINCTRL_IRQEN0 0x800
|
||||
#define HW_PINCTRL_IRQEN1 0x810
|
||||
#define HW_PINCTRL_IRQEN2 0x820
|
||||
|
||||
#define HW_PINCTRL_IRQLEVEL0 0x900
|
||||
#define HW_PINCTRL_IRQLEVEL1 0x910
|
||||
#define HW_PINCTRL_IRQLEVEL2 0x920
|
||||
|
||||
#define HW_PINCTRL_IRQPOL0 0xA00
|
||||
#define HW_PINCTRL_IRQPOL1 0xA10
|
||||
#define HW_PINCTRL_IRQPOL2 0xA20
|
||||
|
||||
#define HW_PINCTRL_IRQSTAT0 0xB00
|
||||
#define HW_PINCTRL_IRQSTAT1 0xB10
|
||||
#define HW_PINCTRL_IRQSTAT2 0xB20
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* stmp37xx: POWER register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_POWER
|
||||
#define _MACH_REGS_POWER
|
||||
|
||||
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
|
||||
|
||||
#define HW_POWER_CTRL 0x0
|
||||
#define BM_POWER_CTRL_CLKGATE 0x40000000
|
||||
|
||||
#define HW_POWER_5VCTRL 0x10
|
||||
|
||||
#define HW_POWER_MINPWR 0x20
|
||||
|
||||
#define HW_POWER_CHARGE 0x30
|
||||
|
||||
#define HW_POWER_VDDDCTRL 0x40
|
||||
|
||||
#define HW_POWER_VDDACTRL 0x50
|
||||
|
||||
#define HW_POWER_VDDIOCTRL 0x60
|
||||
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
|
||||
#define BP_POWER_VDDIOCTRL_TRG 0
|
||||
|
||||
#define HW_POWER_STS 0xB0
|
||||
#define BM_POWER_STS_VBUSVALID 0x00000002
|
||||
#define BM_POWER_STS_BVALID 0x00000004
|
||||
#define BM_POWER_STS_AVALID 0x00000008
|
||||
#define BM_POWER_STS_DC_OK 0x00000100
|
||||
|
||||
#define HW_POWER_RESET 0xE0
|
||||
|
||||
#define HW_POWER_DEBUG 0xF0
|
||||
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
|
||||
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
|
||||
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* stmp37xx: PWM register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
|
||||
|
||||
#define HW_PWM_CTRL 0x0
|
||||
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
|
||||
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
|
||||
|
||||
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
|
||||
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
|
||||
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
|
||||
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_ACTIVEn 0x10
|
||||
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
|
||||
#define BP_PWM_ACTIVEn_ACTIVE 0
|
||||
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
|
||||
#define BP_PWM_ACTIVEn_INACTIVE 16
|
||||
|
||||
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
|
||||
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
|
||||
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
|
||||
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
|
||||
|
||||
#define HW_PWM_PERIODn 0x20
|
||||
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
|
||||
#define BP_PWM_PERIODn_PERIOD 0
|
||||
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
|
||||
#define BP_PWM_PERIODn_ACTIVE_STATE 16
|
||||
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
|
||||
#define BP_PWM_PERIODn_INACTIVE_STATE 18
|
||||
#define BM_PWM_PERIODn_CDIV 0x00700000
|
||||
#define BP_PWM_PERIODn_CDIV 20
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* stmp37xx: RTC register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
|
||||
#define REGS_RTC_PHYS 0x8005C000
|
||||
#define REGS_RTC_SIZE 0x2000
|
||||
|
||||
#define HW_RTC_CTRL 0x0
|
||||
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
|
||||
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
|
||||
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
|
||||
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
|
||||
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
|
||||
|
||||
#define HW_RTC_STAT 0x10
|
||||
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
|
||||
#define BP_RTC_STAT_NEW_REGS 8
|
||||
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
|
||||
#define BP_RTC_STAT_STALE_REGS 16
|
||||
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
|
||||
|
||||
#define HW_RTC_SECONDS 0x30
|
||||
|
||||
#define HW_RTC_ALARM 0x40
|
||||
|
||||
#define HW_RTC_WATCHDOG 0x50
|
||||
|
||||
#define HW_RTC_PERSISTENT0 0x60
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
|
||||
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
|
||||
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
|
||||
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
|
||||
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
|
||||
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
|
||||
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
|
||||
|
||||
#define HW_RTC_PERSISTENT1 0x70
|
||||
|
||||
#define HW_RTC_VERSION 0xD0
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* stmp37xx: SSP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
|
||||
#define REGS_SSP1_PHYS 0x80010000
|
||||
#define REGS_SSP2_PHYS 0x80034000
|
||||
#define REGS_SSP_SIZE 0x2000
|
||||
|
||||
#define HW_SSP_CTRL0 0x0
|
||||
#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_SSP_CTRL0_XFER_COUNT 0
|
||||
#define BM_SSP_CTRL0_ENABLE 0x00010000
|
||||
#define BM_SSP_CTRL0_GET_RESP 0x00020000
|
||||
#define BM_SSP_CTRL0_LONG_RESP 0x00080000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
|
||||
#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
|
||||
#define BP_SSP_CTRL0_BUS_WIDTH 22
|
||||
#define BM_SSP_CTRL0_DATA_XFER 0x01000000
|
||||
#define BM_SSP_CTRL0_READ 0x02000000
|
||||
#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
|
||||
#define BM_SSP_CTRL0_LOCK_CS 0x08000000
|
||||
#define BM_SSP_CTRL0_RUN 0x20000000
|
||||
#define BM_SSP_CTRL0_CLKGATE 0x40000000
|
||||
#define BM_SSP_CTRL0_SFTRST 0x80000000
|
||||
|
||||
#define HW_SSP_CMD0 0x10
|
||||
#define BM_SSP_CMD0_CMD 0x000000FF
|
||||
#define BP_SSP_CMD0_CMD 0
|
||||
#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
|
||||
#define BP_SSP_CMD0_BLOCK_COUNT 8
|
||||
#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
|
||||
#define BP_SSP_CMD0_BLOCK_SIZE 16
|
||||
#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
|
||||
#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
|
||||
#define BP_SSP_CMD1_CMD_ARG 0
|
||||
|
||||
#define HW_SSP_TIMING 0x50
|
||||
#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
|
||||
#define BP_SSP_TIMING_CLOCK_RATE 0
|
||||
#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
|
||||
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
|
||||
#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
|
||||
#define BP_SSP_TIMING_TIMEOUT 16
|
||||
|
||||
#define HW_SSP_CTRL1 0x60
|
||||
#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
|
||||
#define BP_SSP_CTRL1_SSP_MODE 0
|
||||
#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
|
||||
#define BP_SSP_CTRL1_WORD_LENGTH 4
|
||||
#define BM_SSP_CTRL1_POLARITY 0x00000200
|
||||
#define BM_SSP_CTRL1_PHASE 0x00000400
|
||||
#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
|
||||
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
|
||||
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
|
||||
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
|
||||
#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
|
||||
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
|
||||
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
|
||||
#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
|
||||
#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
|
||||
|
||||
#define HW_SSP_DATA 0x70
|
||||
|
||||
#define HW_SSP_SDRESP0 0x80
|
||||
|
||||
#define HW_SSP_SDRESP1 0x90
|
||||
|
||||
#define HW_SSP_SDRESP2 0xA0
|
||||
|
||||
#define HW_SSP_SDRESP3 0xB0
|
||||
|
||||
#define HW_SSP_STATUS 0xC0
|
||||
#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
|
||||
#define BM_SSP_STATUS_TIMEOUT 0x00001000
|
||||
#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
|
||||
#define BM_SSP_STATUS_RESP_ERR 0x00008000
|
||||
#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
|
||||
#define BM_SSP_STATUS_CARD_DETECT 0x10000000
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* stmp37xx: TIMROT register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _MACH_REGS_TIMROT
|
||||
#define _MACH_REGS_TIMROT
|
||||
|
||||
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
|
||||
|
||||
#define HW_TIMROT_ROTCTRL 0x0
|
||||
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
|
||||
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCTRLn 0x20
|
||||
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
|
||||
#define BP_TIMROT_TIMCTRLn_SELECT 0
|
||||
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
|
||||
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
|
||||
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
|
||||
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
|
||||
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
|
||||
|
||||
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
|
||||
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
|
||||
|
||||
#define HW_TIMROT_TIMCOUNTn 0x30
|
||||
#endif
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* stmp37xx: UARTAPP register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
|
||||
#define REGS_UARTAPP1_PHYS 0x8006C000
|
||||
#define REGS_UARTAPP_SIZE 0x2000
|
||||
|
||||
#define HW_UARTAPP_CTRL0 0x0
|
||||
#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL0_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
|
||||
#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
|
||||
#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
|
||||
#define BM_UARTAPP_CTRL0_RUN 0x20000000
|
||||
#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
|
||||
#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_CTRL1_XFER_COUNT 0
|
||||
#define BM_UARTAPP_CTRL1_RUN 0x10000000
|
||||
|
||||
#define HW_UARTAPP_CTRL2 0x20
|
||||
#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
|
||||
#define BP_UARTAPP_CTRL2_UARTEN 0
|
||||
#define BM_UARTAPP_CTRL2_TXE 0x00000100
|
||||
#define BM_UARTAPP_CTRL2_RXE 0x00000200
|
||||
#define BM_UARTAPP_CTRL2_RTS 0x00000800
|
||||
#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
|
||||
#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
|
||||
#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
|
||||
#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
|
||||
#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
|
||||
|
||||
#define HW_UARTAPP_LINECTRL 0x30
|
||||
#define BM_UARTAPP_LINECTRL_BRK 0x00000001
|
||||
#define BP_UARTAPP_LINECTRL_BRK 0
|
||||
#define BM_UARTAPP_LINECTRL_PEN 0x00000002
|
||||
#define BM_UARTAPP_LINECTRL_EPS 0x00000004
|
||||
#define BM_UARTAPP_LINECTRL_STP2 0x00000008
|
||||
#define BM_UARTAPP_LINECTRL_FEN 0x00000010
|
||||
#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
|
||||
#define BP_UARTAPP_LINECTRL_WLEN 5
|
||||
#define BM_UARTAPP_LINECTRL_SPS 0x00000080
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
|
||||
#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
|
||||
#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
|
||||
|
||||
#define HW_UARTAPP_INTR 0x50
|
||||
#define BM_UARTAPP_INTR_CTSMIS 0x00000002
|
||||
#define BM_UARTAPP_INTR_RTIS 0x00000040
|
||||
#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
|
||||
#define BM_UARTAPP_INTR_RXIEN 0x00100000
|
||||
#define BM_UARTAPP_INTR_RTIEN 0x00400000
|
||||
|
||||
#define HW_UARTAPP_DATA 0x60
|
||||
|
||||
#define HW_UARTAPP_STAT 0x70
|
||||
#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
|
||||
#define BP_UARTAPP_STAT_RXCOUNT 0
|
||||
#define BM_UARTAPP_STAT_FERR 0x00010000
|
||||
#define BM_UARTAPP_STAT_PERR 0x00020000
|
||||
#define BM_UARTAPP_STAT_BERR 0x00040000
|
||||
#define BM_UARTAPP_STAT_OERR 0x00080000
|
||||
#define BM_UARTAPP_STAT_RXFE 0x01000000
|
||||
#define BM_UARTAPP_STAT_TXFF 0x02000000
|
||||
#define BM_UARTAPP_STAT_TXFE 0x08000000
|
||||
#define BM_UARTAPP_STAT_CTS 0x10000000
|
||||
|
||||
#define HW_UARTAPP_VERSION 0x90
|
||||
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* stmp378x: UARTDBG register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
|
||||
#define REGS_UARTDBG_PHYS 0x80070000
|
||||
#define REGS_UARTDBG_SIZE 0x2000
|
||||
|
||||
#define HW_UARTDBGDR 0x00000000
|
||||
#define BP_UARTDBGDR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDR_RESERVED 12
|
||||
#define BM_UARTDBGDR_RESERVED 0x0000F000
|
||||
#define BF_UARTDBGDR_RESERVED(v) \
|
||||
(((v) << 12) & BM_UARTDBGDR_RESERVED)
|
||||
#define BM_UARTDBGDR_OE 0x00000800
|
||||
#define BM_UARTDBGDR_BE 0x00000400
|
||||
#define BM_UARTDBGDR_PE 0x00000200
|
||||
#define BM_UARTDBGDR_FE 0x00000100
|
||||
#define BP_UARTDBGDR_DATA 0
|
||||
#define BM_UARTDBGDR_DATA 0x000000FF
|
||||
#define BF_UARTDBGDR_DATA(v) \
|
||||
(((v) << 0) & BM_UARTDBGDR_DATA)
|
||||
#define HW_UARTDBGRSR_ECR 0x00000004
|
||||
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
|
||||
#define BP_UARTDBGRSR_ECR_EC 4
|
||||
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
|
||||
#define BF_UARTDBGRSR_ECR_EC(v) \
|
||||
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
|
||||
#define BM_UARTDBGRSR_ECR_OE 0x00000008
|
||||
#define BM_UARTDBGRSR_ECR_BE 0x00000004
|
||||
#define BM_UARTDBGRSR_ECR_PE 0x00000002
|
||||
#define BM_UARTDBGRSR_ECR_FE 0x00000001
|
||||
#define HW_UARTDBGFR 0x00000018
|
||||
#define BP_UARTDBGFR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGFR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
|
||||
#define BP_UARTDBGFR_RESERVED 9
|
||||
#define BM_UARTDBGFR_RESERVED 0x0000FE00
|
||||
#define BF_UARTDBGFR_RESERVED(v) \
|
||||
(((v) << 9) & BM_UARTDBGFR_RESERVED)
|
||||
#define BM_UARTDBGFR_RI 0x00000100
|
||||
#define BM_UARTDBGFR_TXFE 0x00000080
|
||||
#define BM_UARTDBGFR_RXFF 0x00000040
|
||||
#define BM_UARTDBGFR_TXFF 0x00000020
|
||||
#define BM_UARTDBGFR_RXFE 0x00000010
|
||||
#define BM_UARTDBGFR_BUSY 0x00000008
|
||||
#define BM_UARTDBGFR_DCD 0x00000004
|
||||
#define BM_UARTDBGFR_DSR 0x00000002
|
||||
#define BM_UARTDBGFR_CTS 0x00000001
|
||||
#define HW_UARTDBGILPR 0x00000020
|
||||
#define BP_UARTDBGILPR_UNAVAILABLE 8
|
||||
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
|
||||
#define BP_UARTDBGILPR_ILPDVSR 0
|
||||
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
|
||||
#define BF_UARTDBGILPR_ILPDVSR(v) \
|
||||
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
|
||||
#define HW_UARTDBGIBRD 0x00000024
|
||||
#define BP_UARTDBGIBRD_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
|
||||
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
|
||||
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
|
||||
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
|
||||
#define HW_UARTDBGFBRD 0x00000028
|
||||
#define BP_UARTDBGFBRD_UNAVAILABLE 8
|
||||
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
|
||||
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
|
||||
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
|
||||
#define BP_UARTDBGFBRD_RESERVED 6
|
||||
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
|
||||
#define BF_UARTDBGFBRD_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
|
||||
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
|
||||
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
|
||||
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
|
||||
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
|
||||
#define HW_UARTDBGLCR_H 0x0000002c
|
||||
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
|
||||
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
|
||||
#define BP_UARTDBGLCR_H_RESERVED 8
|
||||
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
|
||||
#define BF_UARTDBGLCR_H_RESERVED(v) \
|
||||
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
|
||||
#define BM_UARTDBGLCR_H_SPS 0x00000080
|
||||
#define BP_UARTDBGLCR_H_WLEN 5
|
||||
#define BM_UARTDBGLCR_H_WLEN 0x00000060
|
||||
#define BF_UARTDBGLCR_H_WLEN(v) \
|
||||
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
|
||||
#define BM_UARTDBGLCR_H_FEN 0x00000010
|
||||
#define BM_UARTDBGLCR_H_STP2 0x00000008
|
||||
#define BM_UARTDBGLCR_H_EPS 0x00000004
|
||||
#define BM_UARTDBGLCR_H_PEN 0x00000002
|
||||
#define BM_UARTDBGLCR_H_BRK 0x00000001
|
||||
#define HW_UARTDBGCR 0x00000030
|
||||
#define BP_UARTDBGCR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGCR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
|
||||
#define BM_UARTDBGCR_CTSEN 0x00008000
|
||||
#define BM_UARTDBGCR_RTSEN 0x00004000
|
||||
#define BM_UARTDBGCR_OUT2 0x00002000
|
||||
#define BM_UARTDBGCR_OUT1 0x00001000
|
||||
#define BM_UARTDBGCR_RTS 0x00000800
|
||||
#define BM_UARTDBGCR_DTR 0x00000400
|
||||
#define BM_UARTDBGCR_RXE 0x00000200
|
||||
#define BM_UARTDBGCR_TXE 0x00000100
|
||||
#define BM_UARTDBGCR_LBE 0x00000080
|
||||
#define BP_UARTDBGCR_RESERVED 3
|
||||
#define BM_UARTDBGCR_RESERVED 0x00000078
|
||||
#define BF_UARTDBGCR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGCR_RESERVED)
|
||||
#define BM_UARTDBGCR_SIRLP 0x00000004
|
||||
#define BM_UARTDBGCR_SIREN 0x00000002
|
||||
#define BM_UARTDBGCR_UARTEN 0x00000001
|
||||
#define HW_UARTDBGIFLS 0x00000034
|
||||
#define BP_UARTDBGIFLS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
|
||||
#define BP_UARTDBGIFLS_RESERVED 6
|
||||
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
|
||||
#define BF_UARTDBGIFLS_RESERVED(v) \
|
||||
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
|
||||
#define BP_UARTDBGIFLS_RXIFLSEL 3
|
||||
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
|
||||
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
|
||||
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
|
||||
#define BP_UARTDBGIFLS_TXIFLSEL 0
|
||||
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
|
||||
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
|
||||
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
|
||||
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
|
||||
#define HW_UARTDBGIMSC 0x00000038
|
||||
#define BP_UARTDBGIMSC_UNAVAILABLE 16
|
||||
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
|
||||
#define BP_UARTDBGIMSC_RESERVED 11
|
||||
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGIMSC_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
|
||||
#define BM_UARTDBGIMSC_OEIM 0x00000400
|
||||
#define BM_UARTDBGIMSC_BEIM 0x00000200
|
||||
#define BM_UARTDBGIMSC_PEIM 0x00000100
|
||||
#define BM_UARTDBGIMSC_FEIM 0x00000080
|
||||
#define BM_UARTDBGIMSC_RTIM 0x00000040
|
||||
#define BM_UARTDBGIMSC_TXIM 0x00000020
|
||||
#define BM_UARTDBGIMSC_RXIM 0x00000010
|
||||
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
|
||||
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
|
||||
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
|
||||
#define BM_UARTDBGIMSC_RIMIM 0x00000001
|
||||
#define HW_UARTDBGRIS 0x0000003c
|
||||
#define BP_UARTDBGRIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGRIS_RESERVED 11
|
||||
#define BM_UARTDBGRIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGRIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
|
||||
#define BM_UARTDBGRIS_OERIS 0x00000400
|
||||
#define BM_UARTDBGRIS_BERIS 0x00000200
|
||||
#define BM_UARTDBGRIS_PERIS 0x00000100
|
||||
#define BM_UARTDBGRIS_FERIS 0x00000080
|
||||
#define BM_UARTDBGRIS_RTRIS 0x00000040
|
||||
#define BM_UARTDBGRIS_TXRIS 0x00000020
|
||||
#define BM_UARTDBGRIS_RXRIS 0x00000010
|
||||
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
|
||||
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
|
||||
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
|
||||
#define BM_UARTDBGRIS_RIRMIS 0x00000001
|
||||
#define HW_UARTDBGMIS 0x00000040
|
||||
#define BP_UARTDBGMIS_UNAVAILABLE 16
|
||||
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
|
||||
#define BP_UARTDBGMIS_RESERVED 11
|
||||
#define BM_UARTDBGMIS_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGMIS_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
|
||||
#define BM_UARTDBGMIS_OEMIS 0x00000400
|
||||
#define BM_UARTDBGMIS_BEMIS 0x00000200
|
||||
#define BM_UARTDBGMIS_PEMIS 0x00000100
|
||||
#define BM_UARTDBGMIS_FEMIS 0x00000080
|
||||
#define BM_UARTDBGMIS_RTMIS 0x00000040
|
||||
#define BM_UARTDBGMIS_TXMIS 0x00000020
|
||||
#define BM_UARTDBGMIS_RXMIS 0x00000010
|
||||
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
|
||||
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
|
||||
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
|
||||
#define BM_UARTDBGMIS_RIMMIS 0x00000001
|
||||
#define HW_UARTDBGICR 0x00000044
|
||||
#define BP_UARTDBGICR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGICR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
|
||||
#define BP_UARTDBGICR_RESERVED 11
|
||||
#define BM_UARTDBGICR_RESERVED 0x0000F800
|
||||
#define BF_UARTDBGICR_RESERVED(v) \
|
||||
(((v) << 11) & BM_UARTDBGICR_RESERVED)
|
||||
#define BM_UARTDBGICR_OEIC 0x00000400
|
||||
#define BM_UARTDBGICR_BEIC 0x00000200
|
||||
#define BM_UARTDBGICR_PEIC 0x00000100
|
||||
#define BM_UARTDBGICR_FEIC 0x00000080
|
||||
#define BM_UARTDBGICR_RTIC 0x00000040
|
||||
#define BM_UARTDBGICR_TXIC 0x00000020
|
||||
#define BM_UARTDBGICR_RXIC 0x00000010
|
||||
#define BM_UARTDBGICR_DSRMIC 0x00000008
|
||||
#define BM_UARTDBGICR_DCDMIC 0x00000004
|
||||
#define BM_UARTDBGICR_CTSMIC 0x00000002
|
||||
#define BM_UARTDBGICR_RIMIC 0x00000001
|
||||
#define HW_UARTDBGDMACR 0x00000048
|
||||
#define BP_UARTDBGDMACR_UNAVAILABLE 16
|
||||
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
|
||||
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
|
||||
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
|
||||
#define BP_UARTDBGDMACR_RESERVED 3
|
||||
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
|
||||
#define BF_UARTDBGDMACR_RESERVED(v) \
|
||||
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
|
||||
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
|
||||
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
|
||||
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* stmp37xx: USBCTL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
|
||||
#define REGS_USBCTL_PHYS 0x80000
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* stmp37xx: USBCTRL register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
|
||||
#define REGS_USBCTRL_PHYS 0x80080000
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* stmp37xx: USBPHY register definitions
|
||||
*
|
||||
* Copyright (c) 2008 Freescale Semiconductor
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
|
||||
|
||||
#define HW_USBPHY_PWD 0x0
|
||||
|
||||
#define HW_USBPHY_CTRL 0x30
|
||||
#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
|
||||
#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
|
||||
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
|
||||
#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
|
||||
#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
|
||||
#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
|
||||
#define BM_USBPHY_CTRL_CLKGATE 0x40000000
|
||||
#define BM_USBPHY_CTRL_SFTRST 0x80000000
|
||||
|
||||
#define HW_USBPHY_STATUS 0x40
|
||||
#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
|
||||
#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Freescale STMP37XX platform support
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
#include <mach/platform.h>
|
||||
#include <mach/regs-icoll.h>
|
||||
#include <mach/regs-apbh.h>
|
||||
#include <mach/regs-apbx.h>
|
||||
#include "stmp37xx.h"
|
||||
|
||||
/*
|
||||
* IRQ handling
|
||||
*/
|
||||
static void stmp37xx_ack_irq(unsigned int irq)
|
||||
{
|
||||
/* Disable IRQ */
|
||||
stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
|
||||
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
|
||||
|
||||
/* ACK current interrupt */
|
||||
__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
|
||||
|
||||
/* Barrier */
|
||||
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
|
||||
}
|
||||
|
||||
static void stmp37xx_mask_irq(unsigned int irq)
|
||||
{
|
||||
/* IRQ disable */
|
||||
stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
|
||||
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
|
||||
}
|
||||
|
||||
static void stmp37xx_unmask_irq(unsigned int irq)
|
||||
{
|
||||
/* IRQ enable */
|
||||
stmp3xxx_setl(0x04 << ((irq % 4) * 8),
|
||||
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
|
||||
}
|
||||
|
||||
static struct irq_chip stmp37xx_chip = {
|
||||
.ack = stmp37xx_ack_irq,
|
||||
.mask = stmp37xx_mask_irq,
|
||||
.unmask = stmp37xx_unmask_irq,
|
||||
};
|
||||
|
||||
void __init stmp37xx_init_irq(void)
|
||||
{
|
||||
stmp3xxx_init_irq(&stmp37xx_chip);
|
||||
}
|
||||
|
||||
/*
|
||||
* DMA interrupt handling
|
||||
*/
|
||||
void stmp3xxx_arch_dma_enable_interrupt(int channel)
|
||||
{
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
|
||||
REGS_APBH_BASE + HW_APBH_CTRL1);
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
|
||||
REGS_APBX_BASE + HW_APBX_CTRL1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
|
||||
|
||||
void stmp3xxx_arch_dma_clear_interrupt(int channel)
|
||||
{
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
|
||||
REGS_APBH_BASE + HW_APBH_CTRL1);
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
|
||||
REGS_APBX_BASE + HW_APBX_CTRL1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
|
||||
|
||||
int stmp3xxx_arch_dma_is_interrupt(int channel)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
|
||||
(1 << STMP3XXX_DMA_CHANNEL(channel));
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
|
||||
(1 << STMP3XXX_DMA_CHANNEL(channel));
|
||||
break;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
|
||||
|
||||
void stmp3xxx_arch_dma_reset_channel(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
/* Reset channel and wait for it to complete */
|
||||
stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
|
||||
REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
|
||||
(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
|
||||
cpu_relax();
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
|
||||
REGS_APBX_BASE + HW_APBX_CTRL0);
|
||||
while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
|
||||
(chbit << BP_APBX_CTRL0_RESET_CHANNEL))
|
||||
cpu_relax();
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
|
||||
|
||||
void stmp3xxx_arch_dma_freeze(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
|
||||
|
||||
void stmp3xxx_arch_dma_unfreeze(int channel)
|
||||
{
|
||||
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
|
||||
|
||||
/*
|
||||
* The registers are all very closely mapped, so we might as well map them all
|
||||
* with a single mapping
|
||||
*
|
||||
* Logical Physical
|
||||
* f0000000 80000000 On-chip registers
|
||||
* f1000000 00000000 32k on-chip SRAM
|
||||
*/
|
||||
static struct map_desc stmp37xx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = (u32)STMP3XXX_REGS_BASE,
|
||||
.pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
|
||||
.length = SZ_1M,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
{
|
||||
.virtual = (u32)STMP3XXX_OCRAM_BASE,
|
||||
.pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
|
||||
.length = STMP3XXX_OCRAM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
void __init stmp37xx_map_io(void)
|
||||
{
|
||||
iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X internal functions and data declarations
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __MACH_STMP37XX_H
|
||||
#define __MACH_STMP37XX_H
|
||||
|
||||
void stmp37xx_map_io(void);
|
||||
void stmp37xx_init_irq(void);
|
||||
|
||||
#endif /* __MACH_STMP37XX_H */
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Freescale STMP37XX development board support
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/pins.h>
|
||||
#include <mach/pinmux.h>
|
||||
#include "stmp37xx.h"
|
||||
|
||||
/*
|
||||
* List of STMP37xx development board specific devices
|
||||
*/
|
||||
static struct platform_device *stmp37xx_devb_devices[] = {
|
||||
&stmp3xxx_dbguart,
|
||||
&stmp3xxx_appuart,
|
||||
};
|
||||
|
||||
static struct pin_desc dbguart_pins_0[] = {
|
||||
{ PINID_PWM0, PIN_FUN3, },
|
||||
{ PINID_PWM1, PIN_FUN3, },
|
||||
};
|
||||
|
||||
struct pin_desc appuart_pins_0[] = {
|
||||
{ PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
{ PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
|
||||
};
|
||||
|
||||
static struct pin_group appuart_pins[] = {
|
||||
[0] = {
|
||||
.pins = appuart_pins_0,
|
||||
.nr_pins = ARRAY_SIZE(appuart_pins_0),
|
||||
},
|
||||
/* 37xx has the only app uart */
|
||||
};
|
||||
|
||||
static struct pin_group dbguart_pins[] = {
|
||||
[0] = {
|
||||
.pins = dbguart_pins_0,
|
||||
.nr_pins = ARRAY_SIZE(dbguart_pins_0),
|
||||
},
|
||||
};
|
||||
|
||||
static int dbguart_pins_control(int id, int request)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
if (request)
|
||||
r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
|
||||
else
|
||||
stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
|
||||
return r;
|
||||
}
|
||||
|
||||
|
||||
static void __init stmp37xx_devb_init(void)
|
||||
{
|
||||
stmp3xxx_pinmux_init(NR_REAL_IRQS);
|
||||
|
||||
/* Init STMP3xxx platform */
|
||||
stmp3xxx_init();
|
||||
|
||||
stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
|
||||
stmp3xxx_appuart.dev.platform_data = appuart_pins;
|
||||
|
||||
/* Add STMP37xx development board devices */
|
||||
platform_add_devices(stmp37xx_devb_devices,
|
||||
ARRAY_SIZE(stmp37xx_devb_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(STMP37XX, "STMP37XX")
|
||||
.phys_io = 0x80000000,
|
||||
.io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
|
||||
.boot_params = 0x40000100,
|
||||
.map_io = stmp37xx_map_io,
|
||||
.init_irq = stmp37xx_init_irq,
|
||||
.timer = &stmp3xxx_timer,
|
||||
.init_machine = stmp37xx_devb_init,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
if ARCH_STMP3XXX
|
||||
|
||||
menu "Freescale STMP3xxx implementations"
|
||||
|
||||
choice
|
||||
prompt "Select STMP3xxx chip family"
|
||||
|
||||
config ARCH_STMP37XX
|
||||
bool "Freescale SMTP37xx"
|
||||
select CPU_ARM926T
|
||||
---help---
|
||||
STMP37xx refers to 3700 through 3769 chips
|
||||
|
||||
config ARCH_STMP378X
|
||||
bool "Freescale STMP378x"
|
||||
select CPU_ARM926T
|
||||
---help---
|
||||
STMP378x refers to 3780 through 3789 chips
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Select STMP3xxx board type"
|
||||
|
||||
config MACH_STMP37XX
|
||||
depends on ARCH_STMP37XX
|
||||
bool "Freescale STMP37xx development board"
|
||||
|
||||
config MACH_STMP378X
|
||||
depends on ARCH_STMP378X
|
||||
bool "Freescale STMP378x development board"
|
||||
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#
|
||||
# Makefile for the linux kernel.
|
||||
#
|
||||
# Object file lists.
|
||||
obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Clock control driver for Freescale STMP37XX/STMP378X - internal header file
|
||||
*
|
||||
* Author: Vitaly Wool <vital@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
|
||||
#define __ARCH_ARM_STMX3XXX_CLOCK_H__
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
struct clk_ops {
|
||||
int (*enable) (struct clk *);
|
||||
int (*disable) (struct clk *);
|
||||
long (*get_rate) (struct clk *);
|
||||
long (*round_rate) (struct clk *, u32);
|
||||
int (*set_rate) (struct clk *, u32);
|
||||
int (*set_parent) (struct clk *, struct clk *);
|
||||
};
|
||||
|
||||
struct clk {
|
||||
struct clk *parent;
|
||||
u32 rate;
|
||||
u32 flags;
|
||||
u8 scale_shift;
|
||||
u8 enable_shift;
|
||||
u8 bypass_shift;
|
||||
u8 busy_bit;
|
||||
s8 usage;
|
||||
int enable_wait;
|
||||
int enable_negate;
|
||||
u32 saved_div;
|
||||
void __iomem *enable_reg;
|
||||
void __iomem *scale_reg;
|
||||
void __iomem *bypass_reg;
|
||||
void __iomem *busy_reg;
|
||||
struct clk_ops *ops;
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
/* Flags */
|
||||
#define RATE_PROPAGATES (1<<0)
|
||||
#define NEEDS_INITIALIZATION (1<<1)
|
||||
#define PARENT_SET_RATE (1<<2)
|
||||
#define FIXED_RATE (1<<3)
|
||||
#define ENABLED (1<<4)
|
||||
#define NEEDS_SET_PARENT (1<<5)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X core routines
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/regs-clkctrl.h>
|
||||
|
||||
static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
|
||||
{
|
||||
u32 c;
|
||||
int timeout;
|
||||
|
||||
/* the process of software reset of IP block is done
|
||||
in several steps:
|
||||
|
||||
- clear SFTRST and wait for block is enabled;
|
||||
- clear clock gating (CLKGATE bit);
|
||||
- set the SFTRST again and wait for block is in reset;
|
||||
- clear SFTRST and wait for reset completion.
|
||||
*/
|
||||
c = __raw_readl(hwreg);
|
||||
c &= ~(1<<31); /* clear SFTRST */
|
||||
__raw_writel(c, hwreg);
|
||||
for (timeout = 1000000; timeout > 0; timeout--)
|
||||
/* still in SFTRST state ? */
|
||||
if ((__raw_readl(hwreg) & (1<<31)) == 0)
|
||||
break;
|
||||
if (timeout <= 0) {
|
||||
printk(KERN_ERR"%s(%p): timeout when enabling\n",
|
||||
__func__, hwreg);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
c = __raw_readl(hwreg);
|
||||
c &= ~(1<<30); /* clear CLKGATE */
|
||||
__raw_writel(c, hwreg);
|
||||
|
||||
if (!just_enable) {
|
||||
c = __raw_readl(hwreg);
|
||||
c |= (1<<31); /* now again set SFTRST */
|
||||
__raw_writel(c, hwreg);
|
||||
for (timeout = 1000000; timeout > 0; timeout--)
|
||||
/* poll until CLKGATE set */
|
||||
if (__raw_readl(hwreg) & (1<<30))
|
||||
break;
|
||||
if (timeout <= 0) {
|
||||
printk(KERN_ERR"%s(%p): timeout when resetting\n",
|
||||
__func__, hwreg);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
c = __raw_readl(hwreg);
|
||||
c &= ~(1<<31); /* clear SFTRST */
|
||||
__raw_writel(c, hwreg);
|
||||
for (timeout = 1000000; timeout > 0; timeout--)
|
||||
/* still in SFTRST state ? */
|
||||
if ((__raw_readl(hwreg) & (1<<31)) == 0)
|
||||
break;
|
||||
if (timeout <= 0) {
|
||||
printk(KERN_ERR"%s(%p): timeout when enabling "
|
||||
"after reset\n", __func__, hwreg);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
c = __raw_readl(hwreg);
|
||||
c &= ~(1<<30); /* clear CLKGATE */
|
||||
__raw_writel(c, hwreg);
|
||||
}
|
||||
for (timeout = 1000000; timeout > 0; timeout--)
|
||||
/* still in SFTRST state ? */
|
||||
if ((__raw_readl(hwreg) & (1<<30)) == 0)
|
||||
break;
|
||||
|
||||
if (timeout <= 0) {
|
||||
printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
|
||||
__func__, hwreg);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
|
||||
{
|
||||
int try = 10;
|
||||
int r;
|
||||
|
||||
while (try--) {
|
||||
r = __stmp3xxx_reset_block(hwreg, just_enable);
|
||||
if (!r)
|
||||
break;
|
||||
pr_debug("%s: try %d failed\n", __func__, 10 - try);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_reset_block);
|
||||
|
||||
struct platform_device stmp3xxx_dbguart = {
|
||||
.name = "stmp3xxx-dbguart",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
void __init stmp3xxx_init(void)
|
||||
{
|
||||
/* Turn off auto-slow and other tricks */
|
||||
stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
|
||||
|
||||
stmp3xxx_dma_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X platform devices
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
|
||||
#include <mach/dma.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/stmp3xxx.h>
|
||||
#include <mach/regs-lcdif.h>
|
||||
#include <mach/regs-uartapp.h>
|
||||
#include <mach/regs-gpmi.h>
|
||||
#include <mach/regs-usbctrl.h>
|
||||
#include <mach/regs-ssp.h>
|
||||
#include <mach/regs-rtc.h>
|
||||
|
||||
static u64 common_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct resource appuart_resources[] = {
|
||||
{
|
||||
.start = IRQ_UARTAPP_INTERNAL,
|
||||
.end = IRQ_UARTAPP_INTERNAL,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = IRQ_UARTAPP_RX_DMA,
|
||||
.end = IRQ_UARTAPP_RX_DMA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = IRQ_UARTAPP_TX_DMA,
|
||||
.end = IRQ_UARTAPP_TX_DMA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = REGS_UARTAPP1_PHYS,
|
||||
.end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
/* Rx DMA channel */
|
||||
.start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
|
||||
.end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
|
||||
.flags = IORESOURCE_DMA,
|
||||
}, {
|
||||
/* Tx DMA channel */
|
||||
.start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
|
||||
.end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_appuart = {
|
||||
.name = "stmp3xxx-appuart",
|
||||
.id = 0,
|
||||
.resource = appuart_resources,
|
||||
.num_resources = ARRAY_SIZE(appuart_resources),
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_watchdog = {
|
||||
.name = "stmp3xxx_wdt",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct resource ts_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_TOUCH_DETECT,
|
||||
.end = IRQ_TOUCH_DETECT,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_LRADC_CH5,
|
||||
.end = IRQ_LRADC_CH5,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_touchscreen = {
|
||||
.name = "stmp3xxx_ts",
|
||||
.id = -1,
|
||||
.resource = ts_resource,
|
||||
.num_resources = ARRAY_SIZE(ts_resource),
|
||||
};
|
||||
|
||||
/*
|
||||
* Keypad device
|
||||
*/
|
||||
struct platform_device stmp3xxx_keyboard = {
|
||||
.name = "stmp3xxx-keyboard",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct resource gpmi_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = REGS_GPMI_PHYS,
|
||||
.end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_GPMI_DMA,
|
||||
.end = IRQ_GPMI_DMA,
|
||||
}, {
|
||||
.flags = IORESOURCE_DMA,
|
||||
.start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
|
||||
.end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_gpmi = {
|
||||
.name = "gpmi",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = gpmi_resources,
|
||||
.num_resources = ARRAY_SIZE(gpmi_resources),
|
||||
};
|
||||
|
||||
static struct resource mmc1_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = REGS_SSP1_PHYS,
|
||||
.end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
|
||||
}, {
|
||||
.flags = IORESOURCE_DMA,
|
||||
.start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
|
||||
.end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_SSP1_DMA,
|
||||
.end = IRQ_SSP1_DMA,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_SSP_ERROR,
|
||||
.end = IRQ_SSP_ERROR,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_mmc = {
|
||||
.name = "stmp3xxx-mmc",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = mmc1_resource,
|
||||
.num_resources = ARRAY_SIZE(mmc1_resource),
|
||||
};
|
||||
|
||||
static struct resource usb_resources[] = {
|
||||
{
|
||||
.start = REGS_USBCTRL_PHYS,
|
||||
.end = REGS_USBCTRL_PHYS + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_USB_CTRL,
|
||||
.end = IRQ_USB_CTRL,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_udc = {
|
||||
.name = "fsl-usb2-udc",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = usb_resources,
|
||||
.num_resources = ARRAY_SIZE(usb_resources),
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_ehci = {
|
||||
.name = "fsl-ehci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = usb_resources,
|
||||
.num_resources = ARRAY_SIZE(usb_resources),
|
||||
};
|
||||
|
||||
static struct resource rtc_resources[] = {
|
||||
{
|
||||
.start = REGS_RTC_PHYS,
|
||||
.end = REGS_RTC_PHYS + REGS_RTC_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_RTC_ALARM,
|
||||
.end = IRQ_RTC_ALARM,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = IRQ_RTC_1MSEC,
|
||||
.end = IRQ_RTC_1MSEC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_rtc = {
|
||||
.name = "stmp3xxx-rtc",
|
||||
.id = -1,
|
||||
.resource = rtc_resources,
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
};
|
||||
|
||||
static struct resource ssp1_resources[] = {
|
||||
{
|
||||
.start = REGS_SSP1_PHYS,
|
||||
.end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_SSP1_DMA,
|
||||
.end = IRQ_SSP1_DMA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
|
||||
.end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource ssp2_resources[] = {
|
||||
{
|
||||
.start = REGS_SSP2_PHYS,
|
||||
.end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_SSP2_DMA,
|
||||
.end = IRQ_SSP2_DMA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
|
||||
.end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
|
||||
.flags = IORESOURCE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_spi1 = {
|
||||
.name = "stmp3xxx_ssp",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = ssp1_resources,
|
||||
.num_resources = ARRAY_SIZE(ssp1_resources),
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_spi2 = {
|
||||
.name = "stmp3xxx_ssp",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.resource = ssp2_resources,
|
||||
.num_resources = ARRAY_SIZE(ssp2_resources),
|
||||
};
|
||||
|
||||
static struct resource fb_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_LCDIF_DMA,
|
||||
.end = IRQ_LCDIF_DMA,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_LCDIF_ERROR,
|
||||
.end = IRQ_LCDIF_ERROR,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = REGS_LCDIF_PHYS,
|
||||
.end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_framebuffer = {
|
||||
.name = "stmp3xxx-fb",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(fb_resource),
|
||||
.resource = fb_resource,
|
||||
};
|
||||
|
||||
#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
|
||||
static char *cmdline_device_##name; \
|
||||
static int cmdline_device_##name##_setup(char *dev) \
|
||||
{ \
|
||||
cmdline_device_##name = dev + 1; \
|
||||
return 0; \
|
||||
} \
|
||||
__setup(#name, cmdline_device_##name##_setup); \
|
||||
int stmp3xxx_##name##_device_register(void) \
|
||||
{ \
|
||||
struct platform_device *d = NULL; \
|
||||
if (!cmdline_device_##name || \
|
||||
!strcmp(cmdline_device_##name, #dev1)) \
|
||||
d = &stmp3xxx_##dev1; \
|
||||
else if (!strcmp(cmdline_device_##name, #dev2)) \
|
||||
d = &stmp3xxx_##dev2; \
|
||||
else \
|
||||
printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
|
||||
#name, cmdline_device_##name); \
|
||||
return d ? platform_device_register(d) : -ENOENT; \
|
||||
}
|
||||
|
||||
CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
|
||||
CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
|
||||
|
||||
struct platform_device stmp3xxx_backlight = {
|
||||
.name = "stmp3xxx-bl",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_rotdec = {
|
||||
.name = "stmp3xxx-rotdec",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_persistent = {
|
||||
.name = "stmp3xxx-persistent",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_dcp_bootstream = {
|
||||
.name = "stmp3xxx-dcpboot",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource dcp_resources[] = {
|
||||
{
|
||||
.start = IRQ_DCP_VMI,
|
||||
.end = IRQ_DCP_VMI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = IRQ_DCP,
|
||||
.end = IRQ_DCP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_dcp = {
|
||||
.name = "stmp3xxx-dcp",
|
||||
.id = -1,
|
||||
.resource = dcp_resources,
|
||||
.num_resources = ARRAY_SIZE(dcp_resources),
|
||||
.dev = {
|
||||
.dma_mask = &common_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource battery_resource[] = {
|
||||
{
|
||||
.flags = IORESOURCE_IRQ,
|
||||
.start = IRQ_VDD5V,
|
||||
.end = IRQ_VDD5V,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device stmp3xxx_battery = {
|
||||
.name = "stmp3xxx-battery",
|
||||
.resource = battery_resource,
|
||||
.num_resources = ARRAY_SIZE(battery_resource),
|
||||
};
|
||||
|
|
@ -0,0 +1,463 @@
|
|||
/*
|
||||
* DMA helper routines for Freescale STMP37XX/STMP378X
|
||||
*
|
||||
* Author: dmitry pervushin <dpervushin@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmapool.h>
|
||||
#include <linux/sysdev.h>
|
||||
#include <linux/cpufreq.h>
|
||||
|
||||
#include <asm/page.h>
|
||||
|
||||
#include <mach/platform.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/regs-apbx.h>
|
||||
#include <mach/regs-apbh.h>
|
||||
|
||||
static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
|
||||
static const size_t pool_alignment = 8;
|
||||
static struct stmp3xxx_dma_user {
|
||||
void *pool;
|
||||
int inuse;
|
||||
const char *name;
|
||||
} channels[MAX_DMA_CHANNELS];
|
||||
|
||||
#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
|
||||
#define IS_USED(ch) (channels[ch].inuse)
|
||||
|
||||
int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
|
||||
{
|
||||
struct stmp3xxx_dma_user *user;
|
||||
int err = 0;
|
||||
|
||||
user = channels + ch;
|
||||
if (!IS_VALID_CHANNEL(ch)) {
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (IS_USED(ch)) {
|
||||
err = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
/* Create a pool to allocate dma commands from */
|
||||
user->pool = dma_pool_create(name, dev, pool_item_size,
|
||||
pool_alignment, PAGE_SIZE);
|
||||
if (user->pool == NULL) {
|
||||
err = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
user->name = name;
|
||||
user->inuse++;
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_request);
|
||||
|
||||
int stmp3xxx_dma_release(int ch)
|
||||
{
|
||||
struct stmp3xxx_dma_user *user = channels + ch;
|
||||
int err = 0;
|
||||
|
||||
if (!IS_VALID_CHANNEL(ch)) {
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (!IS_USED(ch)) {
|
||||
err = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
BUG_ON(user->pool == NULL);
|
||||
dma_pool_destroy(user->pool);
|
||||
user->inuse--;
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_release);
|
||||
|
||||
int stmp3xxx_dma_read_semaphore(int channel)
|
||||
{
|
||||
int sem = -1;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
|
||||
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
|
||||
sem &= BM_APBH_CHn_SEMA_PHORE;
|
||||
sem >>= BP_APBH_CHn_SEMA_PHORE;
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
|
||||
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
|
||||
sem &= BM_APBX_CHn_SEMA_PHORE;
|
||||
sem >>= BP_APBX_CHn_SEMA_PHORE;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
return sem;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
|
||||
|
||||
int stmp3xxx_dma_allocate_command(int channel,
|
||||
struct stmp3xxx_dma_descriptor *descriptor)
|
||||
{
|
||||
struct stmp3xxx_dma_user *user = channels + channel;
|
||||
int err = 0;
|
||||
|
||||
if (!IS_VALID_CHANNEL(channel)) {
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (!IS_USED(channel)) {
|
||||
err = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
if (descriptor == NULL) {
|
||||
err = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Allocate memory for a command from the buffer */
|
||||
descriptor->command =
|
||||
dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
|
||||
|
||||
/* Check it worked */
|
||||
if (!descriptor->command) {
|
||||
err = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
memset(descriptor->command, 0, pool_item_size);
|
||||
out:
|
||||
WARN_ON(err);
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
|
||||
|
||||
int stmp3xxx_dma_free_command(int channel,
|
||||
struct stmp3xxx_dma_descriptor *descriptor)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
if (!IS_VALID_CHANNEL(channel)) {
|
||||
err = -ENODEV;
|
||||
goto out;
|
||||
}
|
||||
if (!IS_USED(channel)) {
|
||||
err = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Return the command memory to the pool */
|
||||
dma_pool_free(channels[channel].pool, descriptor->command,
|
||||
descriptor->handle);
|
||||
|
||||
/* Initialise descriptor so we're not tempted to use it */
|
||||
descriptor->command = NULL;
|
||||
descriptor->handle = 0;
|
||||
descriptor->virtual_buf_ptr = NULL;
|
||||
descriptor->next_descr = NULL;
|
||||
|
||||
WARN_ON(err);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_free_command);
|
||||
|
||||
void stmp3xxx_dma_go(int channel,
|
||||
struct stmp3xxx_dma_descriptor *head, u32 semaphore)
|
||||
{
|
||||
int ch = STMP3XXX_DMA_CHANNEL(channel);
|
||||
void __iomem *c, *s;
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
|
||||
s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
|
||||
break;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
|
||||
s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set next command */
|
||||
__raw_writel(head->handle, c);
|
||||
/* Set counting semaphore (kicks off transfer). Assumes
|
||||
peripheral has been set up correctly */
|
||||
__raw_writel(semaphore, s);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_go);
|
||||
|
||||
int stmp3xxx_dma_running(int channel)
|
||||
{
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
|
||||
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
|
||||
BM_APBH_CHn_SEMA_PHORE;
|
||||
|
||||
case STMP3XXX_BUS_APBX:
|
||||
return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
|
||||
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
|
||||
BM_APBX_CHn_SEMA_PHORE;
|
||||
default:
|
||||
BUG();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_running);
|
||||
|
||||
/*
|
||||
* Circular dma chain management
|
||||
*/
|
||||
void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < chain->total_count; i++)
|
||||
stmp3xxx_dma_free_command(
|
||||
STMP3XXX_DMA(chain->channel, chain->bus),
|
||||
&chain->chain[i]);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
|
||||
|
||||
int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
|
||||
struct stmp3xxx_dma_descriptor descriptors[],
|
||||
unsigned items)
|
||||
{
|
||||
int i;
|
||||
int err = 0;
|
||||
|
||||
if (items == 0)
|
||||
return err;
|
||||
|
||||
for (i = 0; i < items; i++) {
|
||||
err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
|
||||
if (err) {
|
||||
WARN_ON(err);
|
||||
/*
|
||||
* Couldn't allocate the whole chain.
|
||||
* deallocate what has been allocated
|
||||
*/
|
||||
if (i) {
|
||||
do {
|
||||
stmp3xxx_dma_free_command(ch,
|
||||
&descriptors
|
||||
[i]);
|
||||
} while (i-- >= 0);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/* link them! */
|
||||
if (i > 0) {
|
||||
descriptors[i - 1].next_descr = &descriptors[i];
|
||||
descriptors[i - 1].command->next =
|
||||
descriptors[i].handle;
|
||||
}
|
||||
}
|
||||
|
||||
/* make list circular */
|
||||
descriptors[items - 1].next_descr = &descriptors[0];
|
||||
descriptors[items - 1].command->next = descriptors[0].handle;
|
||||
|
||||
chain->total_count = items;
|
||||
chain->chain = descriptors;
|
||||
chain->free_index = 0;
|
||||
chain->active_index = 0;
|
||||
chain->cooked_index = 0;
|
||||
chain->free_count = items;
|
||||
chain->active_count = 0;
|
||||
chain->cooked_count = 0;
|
||||
chain->bus = STMP3XXX_DMA_BUS(ch);
|
||||
chain->channel = STMP3XXX_DMA_CHANNEL(ch);
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
|
||||
|
||||
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
|
||||
chain->free_index = 0;
|
||||
chain->active_index = 0;
|
||||
chain->cooked_index = 0;
|
||||
chain->free_count = chain->total_count;
|
||||
chain->active_count = 0;
|
||||
chain->cooked_count = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
|
||||
|
||||
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count)
|
||||
{
|
||||
BUG_ON(chain->cooked_count < count);
|
||||
|
||||
chain->cooked_count -= count;
|
||||
chain->cooked_index += count;
|
||||
chain->cooked_index %= chain->total_count;
|
||||
chain->free_count += count;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_free);
|
||||
|
||||
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count)
|
||||
{
|
||||
void __iomem *c;
|
||||
u32 mask_clr, mask;
|
||||
BUG_ON(chain->free_count < count);
|
||||
|
||||
chain->free_count -= count;
|
||||
chain->free_index += count;
|
||||
chain->free_index %= chain->total_count;
|
||||
chain->active_count += count;
|
||||
|
||||
switch (chain->bus) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
|
||||
mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
|
||||
mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
|
||||
mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
|
||||
mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set counting semaphore (kicks off transfer). Assumes
|
||||
peripheral has been set up correctly */
|
||||
stmp3xxx_clearl(mask_clr, c);
|
||||
stmp3xxx_setl(mask, c);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_active);
|
||||
|
||||
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
unsigned cooked;
|
||||
|
||||
cooked = chain->active_count -
|
||||
stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
|
||||
|
||||
chain->active_count -= cooked;
|
||||
chain->active_index += cooked;
|
||||
chain->active_index %= chain->total_count;
|
||||
|
||||
chain->cooked_count += cooked;
|
||||
|
||||
return cooked;
|
||||
}
|
||||
EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
|
||||
|
||||
void stmp3xxx_dma_set_alt_target(int channel, int function)
|
||||
{
|
||||
#if defined(CONFIG_ARCH_STMP37XX)
|
||||
unsigned bits = 4;
|
||||
#elif defined(CONFIG_ARCH_STMP378X)
|
||||
unsigned bits = 2;
|
||||
#else
|
||||
#error wrong arch
|
||||
#endif
|
||||
int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
|
||||
unsigned mask = (1<<bits) - 1;
|
||||
void __iomem *c;
|
||||
|
||||
BUG_ON(function < 0 || function >= (1<<bits));
|
||||
pr_debug("%s: channel = %d, using mask %x, "
|
||||
"shift = %d\n", __func__, channel, mask, shift);
|
||||
|
||||
switch (STMP3XXX_DMA_BUS(channel)) {
|
||||
case STMP3XXX_BUS_APBH:
|
||||
c = REGS_APBH_BASE + HW_APBH_DEVSEL;
|
||||
break;
|
||||
case STMP3XXX_BUS_APBX:
|
||||
c = REGS_APBX_BASE + HW_APBX_DEVSEL;
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
stmp3xxx_clearl(mask << shift, c);
|
||||
stmp3xxx_setl(mask << shift, c);
|
||||
}
|
||||
EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
|
||||
|
||||
void stmp3xxx_dma_suspend(void)
|
||||
{
|
||||
stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
|
||||
}
|
||||
|
||||
void stmp3xxx_dma_resume(void)
|
||||
{
|
||||
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
|
||||
REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
|
||||
REGS_APBX_BASE + HW_APBX_CTRL0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
|
||||
struct dma_notifier_block {
|
||||
struct notifier_block nb;
|
||||
void *data;
|
||||
};
|
||||
|
||||
static int dma_cpufreq_notifier(struct notifier_block *self,
|
||||
unsigned long phase, void *p)
|
||||
{
|
||||
switch (phase) {
|
||||
case CPUFREQ_POSTCHANGE:
|
||||
stmp3xxx_dma_resume();
|
||||
break;
|
||||
|
||||
case CPUFREQ_PRECHANGE:
|
||||
stmp3xxx_dma_suspend();
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct dma_notifier_block dma_cpufreq_nb = {
|
||||
.nb = {
|
||||
.notifier_call = dma_cpufreq_notifier,
|
||||
},
|
||||
};
|
||||
#endif /* CONFIG_CPU_FREQ */
|
||||
|
||||
void __init stmp3xxx_dma_init(void)
|
||||
{
|
||||
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
|
||||
REGS_APBH_BASE + HW_APBH_CTRL0);
|
||||
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
|
||||
REGS_APBX_BASE + HW_APBX_CTRL0);
|
||||
#ifdef CONFIG_CPU_FREQ
|
||||
cpufreq_register_notifier(&dma_cpufreq_nb.nb,
|
||||
CPUFREQ_TRANSITION_NOTIFIER);
|
||||
#endif /* CONFIG_CPU_FREQ */
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_MACH_CLKDEV_H
|
||||
#define __ASM_MACH_CLKDEV_H
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do { } while (0)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X CPU type detection
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_CPU_H
|
||||
#define __ASM_PLAT_CPU_H
|
||||
|
||||
#ifdef CONFIG_ARCH_STMP37XX
|
||||
#define cpu_is_stmp37xx() (1)
|
||||
#else
|
||||
#define cpu_is_stmp37xx() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_STMP378X
|
||||
#define cpu_is_stmp378x() (1)
|
||||
#else
|
||||
#define cpu_is_stmp378x() (0)
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_PLAT_CPU_H */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
.macro addruart,rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
moveq \rx, #0x80000000 @ physical base address
|
||||
addeq \rx, \rx, #0x00070000
|
||||
movne \rx, #0xf0000000 @ virtual base
|
||||
addne \rx, \rx, #0x00070000
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
strb \rd, [\rx, #0] @ data register at 0
|
||||
.endm
|
||||
|
||||
.macro waituart,rd,rx
|
||||
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
|
||||
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
|
||||
bne 1001b
|
||||
.endm
|
||||
|
||||
.macro busyuart,rd,rx
|
||||
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
|
||||
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
|
||||
bne 1001b
|
||||
.endm
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X DMA helper interface
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_STMP3XXX_DMA_H
|
||||
#define __ASM_PLAT_STMP3XXX_DMA_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dmapool.h>
|
||||
|
||||
#if !defined(MAX_PIO_WORDS)
|
||||
#define MAX_PIO_WORDS (15)
|
||||
#endif
|
||||
|
||||
#define STMP3XXX_BUS_APBH 0
|
||||
#define STMP3XXX_BUS_APBX 1
|
||||
#define STMP3XXX_DMA_MAX_CHANNEL 16
|
||||
#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
|
||||
#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
|
||||
#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
|
||||
#define MAX_DMA_ADDRESS 0xffffffff
|
||||
#define MAX_DMA_CHANNELS 32
|
||||
|
||||
struct stmp3xxx_dma_command {
|
||||
u32 next;
|
||||
u32 cmd;
|
||||
union {
|
||||
u32 buf_ptr;
|
||||
u32 alternate;
|
||||
};
|
||||
u32 pio_words[MAX_PIO_WORDS];
|
||||
};
|
||||
|
||||
struct stmp3xxx_dma_descriptor {
|
||||
struct stmp3xxx_dma_command *command;
|
||||
dma_addr_t handle;
|
||||
|
||||
/* The virtual address of the buffer pointer */
|
||||
void *virtual_buf_ptr;
|
||||
/* The next descriptor in a the DMA chain (optional) */
|
||||
struct stmp3xxx_dma_descriptor *next_descr;
|
||||
};
|
||||
|
||||
struct stmp37xx_circ_dma_chain {
|
||||
unsigned total_count;
|
||||
struct stmp3xxx_dma_descriptor *chain;
|
||||
|
||||
unsigned free_index;
|
||||
unsigned free_count;
|
||||
unsigned active_index;
|
||||
unsigned active_count;
|
||||
unsigned cooked_index;
|
||||
unsigned cooked_count;
|
||||
|
||||
int bus;
|
||||
unsigned channel;
|
||||
};
|
||||
|
||||
static inline struct stmp3xxx_dma_descriptor
|
||||
*stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
return &(chain->chain[chain->free_index]);
|
||||
}
|
||||
|
||||
static inline struct stmp3xxx_dma_descriptor
|
||||
*stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
|
||||
{
|
||||
return &(chain->chain[chain->cooked_index]);
|
||||
}
|
||||
|
||||
int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
|
||||
int stmp3xxx_dma_release(int ch);
|
||||
int stmp3xxx_dma_allocate_command(int ch,
|
||||
struct stmp3xxx_dma_descriptor *descriptor);
|
||||
int stmp3xxx_dma_free_command(int ch,
|
||||
struct stmp3xxx_dma_descriptor *descriptor);
|
||||
void stmp3xxx_dma_continue(int channel, u32 semaphore);
|
||||
void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
|
||||
u32 semaphore);
|
||||
int stmp3xxx_dma_running(int ch);
|
||||
int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
|
||||
struct stmp3xxx_dma_descriptor descriptors[],
|
||||
unsigned items);
|
||||
void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
|
||||
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
|
||||
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count);
|
||||
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
|
||||
unsigned count);
|
||||
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
|
||||
int stmp3xxx_dma_read_semaphore(int ch);
|
||||
void stmp3xxx_dma_init(void);
|
||||
void stmp3xxx_dma_set_alt_target(int ch, int target);
|
||||
void stmp3xxx_dma_suspend(void);
|
||||
void stmp3xxx_dma_resume(void);
|
||||
|
||||
/*
|
||||
* STMP37xx and STMP378x have different DMA control
|
||||
* registers layout
|
||||
*/
|
||||
|
||||
void stmp3xxx_arch_dma_freeze(int ch);
|
||||
void stmp3xxx_arch_dma_unfreeze(int ch);
|
||||
void stmp3xxx_arch_dma_reset_channel(int ch);
|
||||
void stmp3xxx_arch_dma_enable_interrupt(int ch);
|
||||
void stmp3xxx_arch_dma_clear_interrupt(int ch);
|
||||
int stmp3xxx_arch_dma_is_interrupt(int ch);
|
||||
|
||||
static inline void stmp3xxx_dma_reset_channel(int ch)
|
||||
{
|
||||
stmp3xxx_arch_dma_reset_channel(ch);
|
||||
}
|
||||
|
||||
|
||||
static inline void stmp3xxx_dma_freeze(int ch)
|
||||
{
|
||||
stmp3xxx_arch_dma_freeze(ch);
|
||||
}
|
||||
|
||||
static inline void stmp3xxx_dma_unfreeze(int ch)
|
||||
{
|
||||
stmp3xxx_arch_dma_unfreeze(ch);
|
||||
}
|
||||
|
||||
static inline void stmp3xxx_dma_enable_interrupt(int ch)
|
||||
{
|
||||
stmp3xxx_arch_dma_enable_interrupt(ch);
|
||||
}
|
||||
|
||||
static inline void stmp3xxx_dma_clear_interrupt(int ch)
|
||||
{
|
||||
stmp3xxx_arch_dma_clear_interrupt(ch);
|
||||
}
|
||||
|
||||
static inline int stmp3xxx_dma_is_interrupt(int ch)
|
||||
{
|
||||
return stmp3xxx_arch_dma_is_interrupt(ch);
|
||||
}
|
||||
|
||||
#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X GPIO interface
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_GPIO_H
|
||||
#define __ASM_PLAT_GPIO_H
|
||||
|
||||
#define ARCH_NR_GPIOS (32 * 3)
|
||||
#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
|
||||
#define gpio_get_value(gpio) __gpio_get_value(gpio)
|
||||
#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* __ASM_PLAT_GPIO_H */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef __MACH_GPMI_H
|
||||
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <mach/regs-gpmi.h>
|
||||
|
||||
struct gpmi_platform_data {
|
||||
void *pins;
|
||||
int nr_parts;
|
||||
struct mtd_partition *parts;
|
||||
const char *part_types[];
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* This file contains the hardware definitions of the Freescale STMP3XXX
|
||||
*
|
||||
* Copyright (C) 2005 Sigmatel Inc
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
/*
|
||||
* Where in virtual memory the IO devices (timers, system controllers
|
||||
* and so on)
|
||||
*/
|
||||
#define IO_BASE 0xF0000000 /* VA of IO */
|
||||
#define IO_SIZE 0x00100000 /* How much? */
|
||||
#define IO_START 0x80000000 /* PA of IO */
|
||||
|
||||
/* macro to get at IO space when running virtually */
|
||||
#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sigmatel Inc
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(a) __typesafe_io(a)
|
||||
#define __mem_pci(a) (a)
|
||||
#define __mem_isa(a) (a)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#define PHYS_OFFSET UL(0x40000000)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef _MACH_MMC_H
|
||||
#define _MACH_MMC_H
|
||||
|
||||
#include <mach/regs-ssp.h>
|
||||
|
||||
struct stmp3xxxmmc_platform_data {
|
||||
int (*get_wp)(void);
|
||||
unsigned long (*setclock)(void __iomem *base, unsigned long);
|
||||
void (*cmd_pullup)(int);
|
||||
int (*hw_init)(void);
|
||||
void (*hw_release)(void);
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X Pin Multiplexing
|
||||
*
|
||||
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __PINMUX_H
|
||||
#define __PINMUX_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
/* Pin definitions */
|
||||
#include "pins.h"
|
||||
#include <mach/pins.h>
|
||||
|
||||
/*
|
||||
* Each pin may be routed up to four different HW interfaces
|
||||
* including GPIO
|
||||
*/
|
||||
enum pin_fun {
|
||||
PIN_FUN1 = 0,
|
||||
PIN_FUN2,
|
||||
PIN_FUN3,
|
||||
PIN_GPIO,
|
||||
};
|
||||
|
||||
/*
|
||||
* Each pin may have different output drive strength in range from
|
||||
* 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
|
||||
*/
|
||||
enum pin_strength {
|
||||
PIN_4MA = 0,
|
||||
PIN_8MA,
|
||||
PIN_12MA,
|
||||
PIN_16MA,
|
||||
PIN_20MA,
|
||||
};
|
||||
|
||||
/*
|
||||
* Each pin can be programmed for 1.8V or 3.3V
|
||||
*/
|
||||
enum pin_voltage {
|
||||
PIN_1_8V = 0,
|
||||
PIN_3_3V,
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure to define a group of pins and their parameters
|
||||
*/
|
||||
struct pin_desc {
|
||||
unsigned id;
|
||||
enum pin_fun fun;
|
||||
enum pin_strength strength;
|
||||
enum pin_voltage voltage;
|
||||
unsigned pullup:1;
|
||||
};
|
||||
|
||||
struct pin_group {
|
||||
struct pin_desc *pins;
|
||||
int nr_pins;
|
||||
};
|
||||
|
||||
/* Set pin drive strength */
|
||||
void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
|
||||
const char *label);
|
||||
|
||||
/* Set pin voltage */
|
||||
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
|
||||
const char *label);
|
||||
|
||||
/* Enable pull-up resistor for a pin */
|
||||
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
|
||||
|
||||
/*
|
||||
* Request a pin ownership, only one module (identified by @label)
|
||||
* may own a pin.
|
||||
*/
|
||||
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
|
||||
|
||||
/* Release pin */
|
||||
void stmp3xxx_release_pin(unsigned id, const char *label);
|
||||
|
||||
void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
|
||||
|
||||
/*
|
||||
* Each bank is associated with a number of registers to control
|
||||
* pin function, drive strength, voltage and pull-up reigster. The
|
||||
* number of registers of a given type depends on the number of bits
|
||||
* describin particular pin.
|
||||
*/
|
||||
#define HW_MUXSEL_NUM 2 /* registers per bank */
|
||||
#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
|
||||
#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
|
||||
#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
|
||||
#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
|
||||
|
||||
#define HW_DRIVE_NUM 4 /* registers per bank */
|
||||
#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
|
||||
#define HW_DRIVE_PIN_NUM 8 /* pins per register */
|
||||
#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
|
||||
#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
|
||||
#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
|
||||
|
||||
|
||||
struct stmp3xxx_pinmux_bank {
|
||||
struct gpio_chip chip;
|
||||
|
||||
/* Pins allocation map */
|
||||
unsigned long pin_map;
|
||||
|
||||
/* Pin owner names */
|
||||
const char *pin_labels[32];
|
||||
|
||||
/* Bank registers */
|
||||
void __iomem *hw_muxsel[HW_MUXSEL_NUM];
|
||||
void __iomem *hw_drive[HW_DRIVE_NUM];
|
||||
void __iomem *hw_pull;
|
||||
|
||||
void __iomem *pin2irq,
|
||||
*irqlevel,
|
||||
*irqpolarity,
|
||||
*irqen,
|
||||
*irqstat;
|
||||
|
||||
/* HW MUXSEL register function bit values */
|
||||
u8 functions[HW_MUXSEL_PINFUN_NUM];
|
||||
|
||||
/*
|
||||
* HW DRIVE register strength bit values:
|
||||
* 0xff - requested strength is not supported for this bank
|
||||
*/
|
||||
u8 strengths[HW_DRIVE_PINDRV_NUM];
|
||||
|
||||
/* GPIO things */
|
||||
void __iomem *hw_gpio_in,
|
||||
*hw_gpio_out,
|
||||
*hw_gpio_doe;
|
||||
int irq, virq;
|
||||
};
|
||||
|
||||
int __init stmp3xxx_pinmux_init(int virtual_irq_start);
|
||||
|
||||
#endif /* __PINMUX_H */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
|
||||
*
|
||||
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_PINS_H
|
||||
#define __ASM_PLAT_PINS_H
|
||||
|
||||
#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
|
||||
#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
|
||||
#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
|
||||
|
||||
/*
|
||||
* Special invalid pin identificator to show a pin doesn't exist
|
||||
*/
|
||||
#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
|
||||
|
||||
#endif /* __ASM_PLAT_PINS_H */
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_PLATFORM_H
|
||||
#define __ASM_PLAT_PLATFORM_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <linux/io.h>
|
||||
#endif
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/* Virtual address where registers are mapped */
|
||||
#define STMP3XXX_REGS_PHBASE 0x80000000
|
||||
#ifdef __ASSEMBLER__
|
||||
#define STMP3XXX_REGS_BASE 0xF0000000
|
||||
#else
|
||||
#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
|
||||
#endif
|
||||
#define STMP3XXX_REGS_SIZE SZ_1M
|
||||
|
||||
/* Virtual address where OCRAM is mapped */
|
||||
#define STMP3XXX_OCRAM_PHBASE 0x00000000
|
||||
#ifdef __ASSEMBLER__
|
||||
#define STMP3XXX_OCRAM_BASE 0xf1000000
|
||||
#else
|
||||
#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
|
||||
#endif
|
||||
#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
|
||||
|
||||
#ifdef CONFIG_ARCH_STMP37XX
|
||||
#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
|
||||
#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_STMP378X
|
||||
#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
|
||||
#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
|
||||
#endif
|
||||
|
||||
#define HW_STMP3XXX_SET 0x04
|
||||
#define HW_STMP3XXX_CLR 0x08
|
||||
#define HW_STMP3XXX_TOG 0x0c
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
|
||||
{
|
||||
__raw_writel(v, r + HW_STMP3XXX_CLR);
|
||||
}
|
||||
|
||||
static inline void stmp3xxx_setl(u32 v, void __iomem *r)
|
||||
{
|
||||
__raw_writel(v, r + HW_STMP3XXX_SET);
|
||||
}
|
||||
#endif
|
||||
|
||||
#define BF(value, field) (((value) << BP_##field) & BM_##field)
|
||||
|
||||
#endif /* __ASM_ARCH_PLATFORM_H */
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* Freescale STMP37XX/STMP378X core structure and function declarations
|
||||
*
|
||||
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_PLAT_STMP3XXX_H
|
||||
#define __ASM_PLAT_STMP3XXX_H
|
||||
|
||||
#include <linux/irq.h>
|
||||
|
||||
extern struct sys_timer stmp3xxx_timer;
|
||||
|
||||
void stmp3xxx_init_irq(struct irq_chip *chip);
|
||||
void stmp3xxx_init(void);
|
||||
int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
|
||||
extern struct platform_device stmp3xxx_dbguart,
|
||||
stmp3xxx_appuart,
|
||||
stmp3xxx_watchdog,
|
||||
stmp3xxx_touchscreen,
|
||||
stmp3xxx_keyboard,
|
||||
stmp3xxx_gpmi,
|
||||
stmp3xxx_mmc,
|
||||
stmp3xxx_udc,
|
||||
stmp3xxx_ehci,
|
||||
stmp3xxx_rtc,
|
||||
stmp3xxx_spi1,
|
||||
stmp3xxx_spi2,
|
||||
stmp3xxx_backlight,
|
||||
stmp3xxx_rotdec,
|
||||
stmp3xxx_dcp,
|
||||
stmp3xxx_dcp_bootstream,
|
||||
stmp3xxx_persistent,
|
||||
stmp3xxx_framebuffer,
|
||||
stmp3xxx_battery;
|
||||
int stmp3xxx_ssp1_device_register(void);
|
||||
int stmp3xxx_ssp2_device_register(void);
|
||||
|
||||
struct pin_group;
|
||||
void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
|
||||
int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
|
||||
|
||||
#endif /* __ASM_PLAT_STMP3XXX_H */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Sigmatel Inc
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include <mach/platform.h>
|
||||
#include <mach/regs-clkctrl.h>
|
||||
#include <mach/regs-power.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks
|
||||
*/
|
||||
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode, const char *cmd)
|
||||
{
|
||||
/* Set BATTCHRG to default value */
|
||||
__raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
|
||||
|
||||
/* Set MINPWR to default value */
|
||||
__raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
|
||||
|
||||
/* Reset digital side of chip (but not power or RTC) */
|
||||
__raw_writel(BM_CLKCTRL_RESET_DIG,
|
||||
REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
|
||||
|
||||
/* Should not return */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* System time clock is sourced from the 32k clock
|
||||
*/
|
||||
#define CLOCK_TICK_RATE (32768)
|
||||
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