Merge remote-tracking branches 'asoc/fix/adsp', 'asoc/fix/davinci', 'asoc/fix/max98090', 'asoc/fix/sigmadsp' and 'asoc/fix/tlv320aic31xx' into asoc-linus
This commit is contained in:
Коммит
063e01a29b
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@ -1311,6 +1311,10 @@ static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
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{"MIC1 Input", NULL, "MIC1"},
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{"MIC2 Input", NULL, "MIC2"},
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{"DMICL", NULL, "DMICL_ENA"},
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{"DMICL", NULL, "DMICR_ENA"},
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{"DMICR", NULL, "DMICL_ENA"},
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{"DMICR", NULL, "DMICR_ENA"},
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{"DMICL", NULL, "AHPF"},
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{"DMICR", NULL, "AHPF"},
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@ -1368,8 +1372,6 @@ static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
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{"DMIC Mux", "ADC", "ADCR"},
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{"DMIC Mux", "DMIC", "DMICL"},
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{"DMIC Mux", "DMIC", "DMICR"},
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{"DMIC Mux", "DMIC", "DMICL_ENA"},
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{"DMIC Mux", "DMIC", "DMICR_ENA"},
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{"LBENL Mux", "Normal", "DMIC Mux"},
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{"LBENL Mux", "Loopback", "LTENL Mux"},
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@ -1395,8 +1397,8 @@ static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
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{"STENL Mux", "Sidetone Left", "DMICL"},
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{"STENR Mux", "Sidetone Right", "ADCR"},
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{"STENR Mux", "Sidetone Right", "DMICR"},
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{"DACL", "NULL", "STENL Mux"},
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{"DACR", "NULL", "STENL Mux"},
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{"DACL", NULL, "STENL Mux"},
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{"DACR", NULL, "STENR Mux"},
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{"AIFINL", NULL, "SHDN"},
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{"AIFINR", NULL, "SHDN"},
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@ -159,6 +159,13 @@ int _process_sigma_firmware(struct device *dev,
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goto done;
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}
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if (ssfw_head->version != 1) {
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dev_err(dev,
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"Failed to load firmware: Invalid version %d. Supported firmware versions: 1\n",
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ssfw_head->version);
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goto done;
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}
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crc = crc32(0, fw->data + sizeof(*ssfw_head),
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fw->size - sizeof(*ssfw_head));
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pr_debug("%s: crc=%x\n", __func__, crc);
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@ -911,12 +911,13 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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}
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aic31xx->p_div = i;
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for (i = 0; aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++) {
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if (i == ARRAY_SIZE(aic31xx_divs)) {
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dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
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__func__, freq);
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(aic31xx_divs) &&
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aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++)
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;
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if (i == ARRAY_SIZE(aic31xx_divs)) {
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dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
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__func__, freq);
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return -EINVAL;
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}
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/* set clock on MCLK, BCLK, or GPIO1 as PLL input */
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@ -1595,13 +1595,6 @@ static void wm_adsp2_boot_work(struct work_struct *work)
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if (ret != 0)
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goto err;
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ret = regmap_update_bits_async(dsp->regmap,
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dsp->base + ADSP2_CONTROL,
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ADSP2_CORE_ENA,
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ADSP2_CORE_ENA);
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if (ret != 0)
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goto err;
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dsp->running = true;
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return;
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@ -1651,8 +1644,8 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
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ret = regmap_update_bits(dsp->regmap,
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dsp->base + ADSP2_CONTROL,
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ADSP2_START,
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ADSP2_START);
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ADSP2_CORE_ENA | ADSP2_START,
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ADSP2_CORE_ENA | ADSP2_START);
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if (ret != 0)
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goto err;
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break;
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@ -154,9 +154,9 @@ static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
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static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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{
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/* Start clocks */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
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/*
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* When ASYNC == 0 the transmit and receive sections operate
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* synchronously from the transmit clock and frame sync. We need to make
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@ -167,47 +167,36 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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}
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/* Activate serializer(s) */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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/* Release RX state machine */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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/* Release Frame Sync generator */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
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if (mcasp_is_synchronous(mcasp))
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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}
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static void mcasp_start_tx(struct davinci_mcasp *mcasp)
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{
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u8 offset = 0, i;
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u32 cnt;
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/* Start clocks */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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/* Activate serializer(s) */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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for (i = 0; i < mcasp->num_serializer; i++) {
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if (mcasp->serial_dir[i] == TX_MODE) {
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offset = i;
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break;
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}
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}
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/* wait for TX ready */
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/* wait for XDATA to be cleared */
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cnt = 0;
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while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
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TXSTATE) && (cnt < 100000))
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while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
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~XRDATA) && (cnt < 100000))
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cnt++;
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
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/* Release TX state machine */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
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/* Release Frame Sync generator */
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
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}
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static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
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@ -244,6 +233,12 @@ static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
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mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
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if (mcasp->rxnumevt) { /* disable FIFO */
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u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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}
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static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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@ -259,27 +254,22 @@ static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
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mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
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mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
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if (mcasp->txnumevt) { /* disable FIFO */
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u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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}
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static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
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{
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u32 reg;
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mcasp->streams--;
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if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (mcasp->txnumevt) { /* disable FIFO */
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reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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if (stream == SNDRV_PCM_STREAM_PLAYBACK)
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mcasp_stop_tx(mcasp);
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} else {
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if (mcasp->rxnumevt) { /* disable FIFO */
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reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
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mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
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}
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else
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mcasp_stop_rx(mcasp);
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}
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}
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static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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@ -500,8 +490,17 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
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* both left and right channels), so it has to be divided by number of
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* tdm-slots (for I2S - divided by 2).
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*/
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if (mcasp->bclk_lrclk_ratio)
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word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
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if (mcasp->bclk_lrclk_ratio) {
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u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
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/*
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* When we have more bclk then it is needed for the data, we
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* need to use the rotation to move the received samples to have
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* correct alignment.
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*/
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rx_rotate = (slot_length - word_length) / 4;
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word_length = slot_length;
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}
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/* mapping of the XSSZ bit-field as described in the datasheet */
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fmt = (word_length >> 1) - 1;
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@ -971,6 +970,7 @@ static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
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},
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.ops = &davinci_mcasp_dai_ops,
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.symmetric_samplebits = 1,
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},
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{
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.name = "davinci-mcasp.1",
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@ -1235,6 +1235,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
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ret = pm_runtime_get_sync(&pdev->dev);
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if (IS_ERR_VALUE(ret)) {
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dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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@ -252,6 +252,12 @@
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#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
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#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
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/*
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* DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
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* DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
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*/
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#define XRDATA BIT(5) /* Transmit/Receive data ready */
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/*
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* DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
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*/
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