net/wan/fsl_ucc_hdlc: add hdlc-bus support
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
c7f235a7c2
Коммит
067bb938da
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@ -98,6 +98,13 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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uf_info->tsa = 1;
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uf_info->ctsp = 1;
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}
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/* This sets HPM register in CMXUCR register which configures a
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* open drain connected HDLC bus
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*/
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if (priv->hdlc_bus)
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uf_info->brkpt_support = 1;
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uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
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UCC_HDLC_UCCE_TXB) << 16);
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@ -135,6 +142,28 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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/* Set UPSMR normal mode (need fixed)*/
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iowrite32be(0, &priv->uf_regs->upsmr);
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/* hdlc_bus mode */
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if (priv->hdlc_bus) {
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u32 upsmr;
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dev_info(priv->dev, "HDLC bus Mode\n");
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upsmr = ioread32be(&priv->uf_regs->upsmr);
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/* bus mode and retransmit enable, with collision window
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* set to 8 bytes
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*/
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upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
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UCC_HDLC_UPSMR_CW8;
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iowrite32be(upsmr, &priv->uf_regs->upsmr);
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/* explicitly disable CDS & CTSP */
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gumr = ioread32be(&priv->uf_regs->gumr);
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gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
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/* set automatic sync to explicitly ignore CD signal */
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gumr |= UCC_FAST_GUMR_SYNL_AUTO;
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iowrite32be(gumr, &priv->uf_regs->gumr);
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}
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priv->rx_ring_size = RX_BD_RING_LEN;
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priv->tx_ring_size = TX_BD_RING_LEN;
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/* Alloc Rx BD */
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@ -1046,6 +1075,9 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
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if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
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uhdlc_priv->loopback = 1;
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if (of_get_property(np, "fsl,hdlc-bus", NULL))
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uhdlc_priv->hdlc_bus = 1;
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if (uhdlc_priv->tsa == 1) {
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utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
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if (!utdm) {
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@ -78,6 +78,7 @@ struct ucc_hdlc_private {
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u16 tsa;
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bool hdlc_busy;
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bool loopback;
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bool hdlc_bus;
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u8 *tx_buffer;
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u8 *rx_buffer;
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@ -789,6 +789,11 @@ struct ucc_slow_pram {
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#define UCC_GETH_UPSMR_SMM 0x00000080
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#define UCC_GETH_UPSMR_SGMM 0x00000020
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/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
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#define UCC_HDLC_UPSMR_RTE 0x02000000
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#define UCC_HDLC_UPSMR_BUS 0x00200000
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#define UCC_HDLC_UPSMR_CW8 0x00007000
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/* UCC Transmit On Demand Register (UTODR) */
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#define UCC_SLOW_TOD 0x8000
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#define UCC_FAST_TOD 0x8000
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