can: sja1000: use common prefix for all sja1000 defines
This is a follow up patch to:
f901b6b can: sja1000: fix define conflict on SH
That patch fixed a define conflict between the SH architecture and the sja1000
driver, by addind a prefix to one macro only. This patch consistently renames
the prefix of the SJA1000 controller registers from "REG_" to "SJA1000_".
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Oliver Hartkopp
Marc Kleine-Budde
Родитель
61f47132dc
Коммит
06e1d1d718
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@ -168,12 +168,12 @@ static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
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unsigned char res;
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/* Make sure SJA1000 is in reset mode */
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priv->write_reg(priv, REG_MOD, 1);
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priv->write_reg(priv, SJA1000_MOD, 1);
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priv->write_reg(priv, REG_CDR, CDR_PELICAN);
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priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
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/* read reset-values */
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res = priv->read_reg(priv, REG_CDR);
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res = priv->read_reg(priv, SJA1000_CDR);
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if (res == CDR_PELICAN)
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return 1;
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@ -126,11 +126,11 @@ static irqreturn_t ems_pcmcia_interrupt(int irq, void *dev_id)
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static inline int ems_pcmcia_check_chan(struct sja1000_priv *priv)
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{
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/* Make sure SJA1000 is in reset mode */
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ems_pcmcia_write_reg(priv, REG_MOD, 1);
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ems_pcmcia_write_reg(priv, REG_CDR, CDR_PELICAN);
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ems_pcmcia_write_reg(priv, SJA1000_MOD, 1);
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ems_pcmcia_write_reg(priv, SJA1000_CDR, CDR_PELICAN);
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/* read reset-values */
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if (ems_pcmcia_read_reg(priv, REG_CDR) == CDR_PELICAN)
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if (ems_pcmcia_read_reg(priv, SJA1000_CDR) == CDR_PELICAN)
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return 1;
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return 0;
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@ -159,9 +159,9 @@ static int number_of_sja1000_chip(void __iomem *base_addr)
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for (i = 0; i < MAX_NO_OF_CHANNELS; i++) {
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/* reset chip */
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iowrite8(MOD_RM, base_addr +
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(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
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(i * KVASER_PCI_PORT_BYTES) + SJA1000_MOD);
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status = ioread8(base_addr +
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(i * KVASER_PCI_PORT_BYTES) + REG_MOD);
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(i * KVASER_PCI_PORT_BYTES) + SJA1000_MOD);
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/* check reset bit */
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if (!(status & MOD_RM))
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break;
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@ -402,7 +402,7 @@ static void peak_pciec_write_reg(const struct sja1000_priv *priv,
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int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE;
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/* sja1000 register changes control the leds state */
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if (port == REG_MOD)
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if (port == SJA1000_MOD)
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switch (val) {
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case MOD_RM:
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/* Reset Mode: set led on */
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@ -196,7 +196,7 @@ static void pcan_write_canreg(const struct sja1000_priv *priv, int port, u8 v)
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int c = (priv->reg_base - card->ioport_addr) / PCC_CHAN_SIZE;
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/* sja1000 register changes control the leds state */
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if (port == REG_MOD)
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if (port == SJA1000_MOD)
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switch (v) {
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case MOD_RM:
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/* Reset Mode: set led on */
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@ -509,11 +509,11 @@ static void pcan_free_channels(struct pcan_pccard *card)
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static inline int pcan_channel_present(struct sja1000_priv *priv)
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{
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/* make sure SJA1000 is in reset mode */
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pcan_write_canreg(priv, REG_MOD, 1);
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pcan_write_canreg(priv, REG_CDR, CDR_PELICAN);
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pcan_write_canreg(priv, SJA1000_MOD, 1);
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pcan_write_canreg(priv, SJA1000_CDR, CDR_PELICAN);
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/* read reset-values */
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if (pcan_read_canreg(priv, REG_CDR) == CDR_PELICAN)
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if (pcan_read_canreg(priv, SJA1000_CDR) == CDR_PELICAN)
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return 1;
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return 0;
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@ -348,20 +348,20 @@ static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
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*/
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if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
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REG_CR_BASICCAN_INITIAL &&
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(priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_BASICCAN_INITIAL) &&
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(priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
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(priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
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(priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
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flag = 1;
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/* Bring the SJA1000 into the PeliCAN mode*/
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priv->write_reg(priv, REG_CDR, CDR_PELICAN);
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priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
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/*
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* Check registers after reset in the PeliCAN mode.
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* See states on p. 23 of the Datasheet.
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*/
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if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
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priv->read_reg(priv, SJA1000_REG_SR) == REG_SR_PELICAN_INITIAL &&
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priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
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if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
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priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
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priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
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return flag;
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return 0;
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@ -91,14 +91,14 @@ static void sja1000_write_cmdreg(struct sja1000_priv *priv, u8 val)
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* the write_reg() operation - especially on SMP systems.
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*/
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spin_lock_irqsave(&priv->cmdreg_lock, flags);
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priv->write_reg(priv, REG_CMR, val);
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priv->read_reg(priv, SJA1000_REG_SR);
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priv->write_reg(priv, SJA1000_CMR, val);
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priv->read_reg(priv, SJA1000_SR);
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spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
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}
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static int sja1000_is_absent(struct sja1000_priv *priv)
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{
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return (priv->read_reg(priv, REG_MOD) == 0xFF);
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return (priv->read_reg(priv, SJA1000_MOD) == 0xFF);
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}
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static int sja1000_probe_chip(struct net_device *dev)
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@ -116,11 +116,11 @@ static int sja1000_probe_chip(struct net_device *dev)
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static void set_reset_mode(struct net_device *dev)
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{
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struct sja1000_priv *priv = netdev_priv(dev);
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unsigned char status = priv->read_reg(priv, REG_MOD);
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unsigned char status = priv->read_reg(priv, SJA1000_MOD);
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int i;
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/* disable interrupts */
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priv->write_reg(priv, REG_IER, IRQ_OFF);
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priv->write_reg(priv, SJA1000_IER, IRQ_OFF);
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for (i = 0; i < 100; i++) {
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/* check reset bit */
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@ -129,9 +129,10 @@ static void set_reset_mode(struct net_device *dev)
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return;
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}
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priv->write_reg(priv, REG_MOD, MOD_RM); /* reset chip */
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/* reset chip */
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priv->write_reg(priv, SJA1000_MOD, MOD_RM);
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udelay(10);
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status = priv->read_reg(priv, REG_MOD);
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status = priv->read_reg(priv, SJA1000_MOD);
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}
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netdev_err(dev, "setting SJA1000 into reset mode failed!\n");
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@ -140,7 +141,7 @@ static void set_reset_mode(struct net_device *dev)
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static void set_normal_mode(struct net_device *dev)
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{
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struct sja1000_priv *priv = netdev_priv(dev);
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unsigned char status = priv->read_reg(priv, REG_MOD);
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unsigned char status = priv->read_reg(priv, SJA1000_MOD);
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int i;
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for (i = 0; i < 100; i++) {
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@ -149,22 +150,22 @@ static void set_normal_mode(struct net_device *dev)
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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/* enable interrupts */
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if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
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priv->write_reg(priv, REG_IER, IRQ_ALL);
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priv->write_reg(priv, SJA1000_IER, IRQ_ALL);
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else
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priv->write_reg(priv, REG_IER,
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priv->write_reg(priv, SJA1000_IER,
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IRQ_ALL & ~IRQ_BEI);
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return;
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}
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/* set chip to normal mode */
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if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
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priv->write_reg(priv, REG_MOD, MOD_LOM);
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priv->write_reg(priv, SJA1000_MOD, MOD_LOM);
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else
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priv->write_reg(priv, REG_MOD, 0x00);
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priv->write_reg(priv, SJA1000_MOD, 0x00);
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udelay(10);
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status = priv->read_reg(priv, REG_MOD);
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status = priv->read_reg(priv, SJA1000_MOD);
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}
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netdev_err(dev, "setting SJA1000 into normal mode failed!\n");
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@ -179,9 +180,9 @@ static void sja1000_start(struct net_device *dev)
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set_reset_mode(dev);
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/* Clear error counters and error code capture */
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priv->write_reg(priv, REG_TXERR, 0x0);
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priv->write_reg(priv, REG_RXERR, 0x0);
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priv->read_reg(priv, REG_ECC);
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priv->write_reg(priv, SJA1000_TXERR, 0x0);
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priv->write_reg(priv, SJA1000_RXERR, 0x0);
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priv->read_reg(priv, SJA1000_ECC);
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/* leave reset mode */
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set_normal_mode(dev);
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@ -217,8 +218,8 @@ static int sja1000_set_bittiming(struct net_device *dev)
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netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
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priv->write_reg(priv, REG_BTR0, btr0);
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priv->write_reg(priv, REG_BTR1, btr1);
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priv->write_reg(priv, SJA1000_BTR0, btr0);
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priv->write_reg(priv, SJA1000_BTR1, btr1);
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return 0;
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}
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@ -228,8 +229,8 @@ static int sja1000_get_berr_counter(const struct net_device *dev,
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{
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struct sja1000_priv *priv = netdev_priv(dev);
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bec->txerr = priv->read_reg(priv, REG_TXERR);
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bec->rxerr = priv->read_reg(priv, REG_RXERR);
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bec->txerr = priv->read_reg(priv, SJA1000_TXERR);
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bec->rxerr = priv->read_reg(priv, SJA1000_RXERR);
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return 0;
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}
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@ -247,20 +248,20 @@ static void chipset_init(struct net_device *dev)
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struct sja1000_priv *priv = netdev_priv(dev);
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/* set clock divider and output control register */
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priv->write_reg(priv, REG_CDR, priv->cdr | CDR_PELICAN);
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priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
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/* set acceptance filter (accept all) */
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priv->write_reg(priv, REG_ACCC0, 0x00);
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priv->write_reg(priv, REG_ACCC1, 0x00);
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priv->write_reg(priv, REG_ACCC2, 0x00);
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priv->write_reg(priv, REG_ACCC3, 0x00);
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priv->write_reg(priv, SJA1000_ACCC0, 0x00);
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priv->write_reg(priv, SJA1000_ACCC1, 0x00);
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priv->write_reg(priv, SJA1000_ACCC2, 0x00);
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priv->write_reg(priv, SJA1000_ACCC3, 0x00);
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priv->write_reg(priv, REG_ACCM0, 0xFF);
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priv->write_reg(priv, REG_ACCM1, 0xFF);
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priv->write_reg(priv, REG_ACCM2, 0xFF);
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priv->write_reg(priv, REG_ACCM3, 0xFF);
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priv->write_reg(priv, SJA1000_ACCM0, 0xFF);
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priv->write_reg(priv, SJA1000_ACCM1, 0xFF);
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priv->write_reg(priv, SJA1000_ACCM2, 0xFF);
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priv->write_reg(priv, SJA1000_ACCM3, 0xFF);
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priv->write_reg(priv, REG_OCR, priv->ocr | OCR_MODE_NORMAL);
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priv->write_reg(priv, SJA1000_OCR, priv->ocr | OCR_MODE_NORMAL);
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}
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/*
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@ -289,21 +290,21 @@ static netdev_tx_t sja1000_start_xmit(struct sk_buff *skb,
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id = cf->can_id;
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if (id & CAN_RTR_FLAG)
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fi |= FI_RTR;
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fi |= SJA1000_FI_RTR;
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if (id & CAN_EFF_FLAG) {
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fi |= FI_FF;
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dreg = EFF_BUF;
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priv->write_reg(priv, REG_FI, fi);
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priv->write_reg(priv, REG_ID1, (id & 0x1fe00000) >> (5 + 16));
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priv->write_reg(priv, REG_ID2, (id & 0x001fe000) >> (5 + 8));
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priv->write_reg(priv, REG_ID3, (id & 0x00001fe0) >> 5);
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priv->write_reg(priv, REG_ID4, (id & 0x0000001f) << 3);
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fi |= SJA1000_FI_FF;
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dreg = SJA1000_EFF_BUF;
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priv->write_reg(priv, SJA1000_FI, fi);
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priv->write_reg(priv, SJA1000_ID1, (id & 0x1fe00000) >> 21);
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priv->write_reg(priv, SJA1000_ID2, (id & 0x001fe000) >> 13);
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priv->write_reg(priv, SJA1000_ID3, (id & 0x00001fe0) >> 5);
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priv->write_reg(priv, SJA1000_ID4, (id & 0x0000001f) << 3);
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} else {
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dreg = SFF_BUF;
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priv->write_reg(priv, REG_FI, fi);
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priv->write_reg(priv, REG_ID1, (id & 0x000007f8) >> 3);
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priv->write_reg(priv, REG_ID2, (id & 0x00000007) << 5);
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dreg = SJA1000_SFF_BUF;
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priv->write_reg(priv, SJA1000_FI, fi);
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priv->write_reg(priv, SJA1000_ID1, (id & 0x000007f8) >> 3);
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priv->write_reg(priv, SJA1000_ID2, (id & 0x00000007) << 5);
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}
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for (i = 0; i < dlc; i++)
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@ -335,25 +336,25 @@ static void sja1000_rx(struct net_device *dev)
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if (skb == NULL)
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return;
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fi = priv->read_reg(priv, REG_FI);
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fi = priv->read_reg(priv, SJA1000_FI);
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if (fi & FI_FF) {
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if (fi & SJA1000_FI_FF) {
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/* extended frame format (EFF) */
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dreg = EFF_BUF;
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id = (priv->read_reg(priv, REG_ID1) << (5 + 16))
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| (priv->read_reg(priv, REG_ID2) << (5 + 8))
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| (priv->read_reg(priv, REG_ID3) << 5)
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| (priv->read_reg(priv, REG_ID4) >> 3);
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dreg = SJA1000_EFF_BUF;
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id = (priv->read_reg(priv, SJA1000_ID1) << 21)
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| (priv->read_reg(priv, SJA1000_ID2) << 13)
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| (priv->read_reg(priv, SJA1000_ID3) << 5)
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| (priv->read_reg(priv, SJA1000_ID4) >> 3);
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id |= CAN_EFF_FLAG;
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} else {
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/* standard frame format (SFF) */
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dreg = SFF_BUF;
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id = (priv->read_reg(priv, REG_ID1) << 3)
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| (priv->read_reg(priv, REG_ID2) >> 5);
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dreg = SJA1000_SFF_BUF;
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id = (priv->read_reg(priv, SJA1000_ID1) << 3)
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| (priv->read_reg(priv, SJA1000_ID2) >> 5);
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}
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cf->can_dlc = get_can_dlc(fi & 0x0F);
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if (fi & FI_RTR) {
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if (fi & SJA1000_FI_RTR) {
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id |= CAN_RTR_FLAG;
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} else {
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for (i = 0; i < cf->can_dlc; i++)
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@ -414,7 +415,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
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priv->can.can_stats.bus_error++;
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stats->rx_errors++;
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ecc = priv->read_reg(priv, REG_ECC);
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ecc = priv->read_reg(priv, SJA1000_ECC);
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cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
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@ -448,7 +449,7 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
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if (isrc & IRQ_ALI) {
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/* arbitration lost interrupt */
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netdev_dbg(dev, "arbitration lost interrupt\n");
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alc = priv->read_reg(priv, REG_ALC);
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alc = priv->read_reg(priv, SJA1000_ALC);
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priv->can.can_stats.arbitration_lost++;
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stats->tx_errors++;
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cf->can_id |= CAN_ERR_LOSTARB;
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@ -457,8 +458,8 @@ static int sja1000_err(struct net_device *dev, uint8_t isrc, uint8_t status)
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if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
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state == CAN_STATE_ERROR_PASSIVE)) {
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uint8_t rxerr = priv->read_reg(priv, REG_RXERR);
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uint8_t txerr = priv->read_reg(priv, REG_TXERR);
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uint8_t rxerr = priv->read_reg(priv, SJA1000_RXERR);
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uint8_t txerr = priv->read_reg(priv, SJA1000_TXERR);
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cf->can_id |= CAN_ERR_CRTL;
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if (state == CAN_STATE_ERROR_WARNING) {
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priv->can.can_stats.error_warning++;
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@ -494,15 +495,16 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
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int n = 0;
|
||||
|
||||
/* Shared interrupts and IRQ off? */
|
||||
if (priv->read_reg(priv, REG_IER) == IRQ_OFF)
|
||||
if (priv->read_reg(priv, SJA1000_IER) == IRQ_OFF)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (priv->pre_irq)
|
||||
priv->pre_irq(priv);
|
||||
|
||||
while ((isrc = priv->read_reg(priv, REG_IR)) && (n < SJA1000_MAX_IRQ)) {
|
||||
while ((isrc = priv->read_reg(priv, SJA1000_IR)) &&
|
||||
(n < SJA1000_MAX_IRQ)) {
|
||||
n++;
|
||||
status = priv->read_reg(priv, SJA1000_REG_SR);
|
||||
status = priv->read_reg(priv, SJA1000_SR);
|
||||
/* check for absent controller due to hw unplug */
|
||||
if (status == 0xFF && sja1000_is_absent(priv))
|
||||
return IRQ_NONE;
|
||||
|
|
@ -519,7 +521,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
|
|||
} else {
|
||||
/* transmission complete */
|
||||
stats->tx_bytes +=
|
||||
priv->read_reg(priv, REG_FI) & 0xf;
|
||||
priv->read_reg(priv, SJA1000_FI) & 0xf;
|
||||
stats->tx_packets++;
|
||||
can_get_echo_skb(dev, 0);
|
||||
}
|
||||
|
|
@ -530,7 +532,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
|
|||
/* receive interrupt */
|
||||
while (status & SR_RBS) {
|
||||
sja1000_rx(dev);
|
||||
status = priv->read_reg(priv, SJA1000_REG_SR);
|
||||
status = priv->read_reg(priv, SJA1000_SR);
|
||||
/* check for absent controller */
|
||||
if (status == 0xFF && sja1000_is_absent(priv))
|
||||
return IRQ_NONE;
|
||||
|
|
|
|||
|
|
@ -54,46 +54,46 @@
|
|||
#define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */
|
||||
|
||||
/* SJA1000 registers - manual section 6.4 (Pelican Mode) */
|
||||
#define REG_MOD 0x00
|
||||
#define REG_CMR 0x01
|
||||
#define SJA1000_REG_SR 0x02
|
||||
#define REG_IR 0x03
|
||||
#define REG_IER 0x04
|
||||
#define REG_ALC 0x0B
|
||||
#define REG_ECC 0x0C
|
||||
#define REG_EWL 0x0D
|
||||
#define REG_RXERR 0x0E
|
||||
#define REG_TXERR 0x0F
|
||||
#define REG_ACCC0 0x10
|
||||
#define REG_ACCC1 0x11
|
||||
#define REG_ACCC2 0x12
|
||||
#define REG_ACCC3 0x13
|
||||
#define REG_ACCM0 0x14
|
||||
#define REG_ACCM1 0x15
|
||||
#define REG_ACCM2 0x16
|
||||
#define REG_ACCM3 0x17
|
||||
#define REG_RMC 0x1D
|
||||
#define REG_RBSA 0x1E
|
||||
#define SJA1000_MOD 0x00
|
||||
#define SJA1000_CMR 0x01
|
||||
#define SJA1000_SR 0x02
|
||||
#define SJA1000_IR 0x03
|
||||
#define SJA1000_IER 0x04
|
||||
#define SJA1000_ALC 0x0B
|
||||
#define SJA1000_ECC 0x0C
|
||||
#define SJA1000_EWL 0x0D
|
||||
#define SJA1000_RXERR 0x0E
|
||||
#define SJA1000_TXERR 0x0F
|
||||
#define SJA1000_ACCC0 0x10
|
||||
#define SJA1000_ACCC1 0x11
|
||||
#define SJA1000_ACCC2 0x12
|
||||
#define SJA1000_ACCC3 0x13
|
||||
#define SJA1000_ACCM0 0x14
|
||||
#define SJA1000_ACCM1 0x15
|
||||
#define SJA1000_ACCM2 0x16
|
||||
#define SJA1000_ACCM3 0x17
|
||||
#define SJA1000_RMC 0x1D
|
||||
#define SJA1000_RBSA 0x1E
|
||||
|
||||
/* Common registers - manual section 6.5 */
|
||||
#define REG_BTR0 0x06
|
||||
#define REG_BTR1 0x07
|
||||
#define REG_OCR 0x08
|
||||
#define REG_CDR 0x1F
|
||||
#define SJA1000_BTR0 0x06
|
||||
#define SJA1000_BTR1 0x07
|
||||
#define SJA1000_OCR 0x08
|
||||
#define SJA1000_CDR 0x1F
|
||||
|
||||
#define REG_FI 0x10
|
||||
#define SFF_BUF 0x13
|
||||
#define EFF_BUF 0x15
|
||||
#define SJA1000_FI 0x10
|
||||
#define SJA1000_SFF_BUF 0x13
|
||||
#define SJA1000_EFF_BUF 0x15
|
||||
|
||||
#define FI_FF 0x80
|
||||
#define FI_RTR 0x40
|
||||
#define SJA1000_FI_FF 0x80
|
||||
#define SJA1000_FI_RTR 0x40
|
||||
|
||||
#define REG_ID1 0x11
|
||||
#define REG_ID2 0x12
|
||||
#define REG_ID3 0x13
|
||||
#define REG_ID4 0x14
|
||||
#define SJA1000_ID1 0x11
|
||||
#define SJA1000_ID2 0x12
|
||||
#define SJA1000_ID3 0x13
|
||||
#define SJA1000_ID4 0x14
|
||||
|
||||
#define CAN_RAM 0x20
|
||||
#define SJA1000_CAN_RAM 0x20
|
||||
|
||||
/* mode register */
|
||||
#define MOD_RM 0x01
|
||||
|
|
|
|||
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