drm/exynos: dp: Use DPCD defines of drm_dp_helper.h
Use DPCD defines of drm_dp_helper.h; thus, duplicated DPCD defines of exynos_dp_core.h can be removed. Also, DP_TEST_EDID_CHECKSUM define is added to drm_dp_helper.h. There is no functional change. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Jingoo Han
Inki Dae
Родитель
96d2653a44
Коммит
073ea2ae85
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@ -144,15 +144,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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return -EIO;
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}
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
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exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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if (test_vector & DP_TEST_LINK_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_EDID_CHECKSUM,
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DP_TEST_EDID_CHECKSUM,
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edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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DP_TEST_RESPONSE,
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DP_TEST_EDID_CHECKSUM_WRITE);
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}
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} else {
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dev_info(dp->dev, "EDID data does not include any extensions.\n");
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@ -174,15 +174,15 @@ static int exynos_dp_read_edid(struct exynos_dp_device *dp)
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}
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exynos_dp_read_byte_from_dpcd(dp,
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DPCD_ADDR_TEST_REQUEST,
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DP_TEST_REQUEST,
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&test_vector);
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if (test_vector & DPCD_TEST_EDID_READ) {
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if (test_vector & DP_TEST_LINK_EDID_READ) {
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_EDID_CHECKSUM,
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DP_TEST_EDID_CHECKSUM,
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edid[EDID_CHECKSUM]);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TEST_RESPONSE,
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DPCD_TEST_EDID_CHECKSUM_WRITE);
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DP_TEST_RESPONSE,
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DP_TEST_EDID_CHECKSUM_WRITE);
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}
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}
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@ -196,8 +196,8 @@ static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
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int i;
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int retval;
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/* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV,
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/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
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retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
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12, buf);
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if (retval)
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return retval;
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@ -217,14 +217,14 @@ static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
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{
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u8 data;
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
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exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
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if (enable)
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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DPCD_ENHANCED_FRAME_EN |
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exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
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DP_LANE_COUNT_ENHANCED_FRAME_EN |
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DPCD_LANE_COUNT_SET(data));
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else
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exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
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DPCD_LANE_COUNT_SET(data));
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}
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@ -233,7 +233,7 @@ static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
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u8 data;
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int retval;
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
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exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
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retval = DPCD_ENHANCED_FRAME_CAP(data);
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return retval;
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@ -253,8 +253,8 @@ static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
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exynos_dp_set_training_pattern(dp, DP_NONE);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_TRAINING_PATTERN_DISABLED);
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DP_TRAINING_PATTERN_SET,
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DP_TRAINING_PATTERN_DISABLE);
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}
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static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
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@ -298,7 +298,7 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
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/* Setup RX configuration */
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buf[0] = dp->link_train.link_rate;
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buf[1] = dp->link_train.lane_count;
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
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retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
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2, buf);
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if (retval)
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return retval;
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@ -325,16 +325,16 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp)
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/* Set RX training pattern */
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retval = exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
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DP_TRAINING_PATTERN_SET,
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DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
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if (retval)
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return retval;
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for (lane = 0; lane < lane_count; lane++)
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buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
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DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
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buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
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DP_TRAIN_VOLTAGE_SWING_400;
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
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retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
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lane_count, buf);
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return retval;
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@ -355,7 +355,7 @@ static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = exynos_dp_get_lane_status(link_status, lane);
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if ((lane_status & DPCD_LANE_CR_DONE) == 0)
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return -EINVAL;
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}
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return 0;
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@ -367,13 +367,13 @@ static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
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int lane;
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u8 lane_status;
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if ((link_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
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if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return -EINVAL;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = exynos_dp_get_lane_status(link_status, lane);
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lane_status &= DPCD_CHANNEL_EQ_BITS;
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if (lane_status != DPCD_CHANNEL_EQ_BITS)
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lane_status &= DP_CHANNEL_EQ_BITS;
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if (lane_status != DP_CHANNEL_EQ_BITS)
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return -EINVAL;
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}
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@ -471,9 +471,9 @@ static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
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DPCD_PRE_EMPHASIS_SET(pre_emphasis);
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if (voltage_swing == VOLTAGE_LEVEL_3)
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training_lane |= DPCD_MAX_SWING_REACHED;
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training_lane |= DP_TRAIN_MAX_SWING_REACHED;
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if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
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training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
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training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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dp->link_train.training_lane[lane] = training_lane;
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}
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@ -490,12 +490,12 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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lane_count = dp->link_train.lane_count;
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
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DP_LANE0_1_STATUS, 2, link_status);
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if (retval)
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return retval;
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
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DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
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if (retval)
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return retval;
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@ -504,9 +504,9 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
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retval = exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DPCD_SCRAMBLING_DISABLED |
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DPCD_TRAINING_PATTERN_2);
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DP_TRAINING_PATTERN_SET,
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DP_LINK_SCRAMBLING_DISABLE |
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DP_TRAINING_PATTERN_2);
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if (retval)
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return retval;
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@ -546,7 +546,7 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
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dp->link_train.training_lane[lane], lane);
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retval = exynos_dp_write_bytes_to_dpcd(dp,
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DPCD_ADDR_TRAINING_LANE0_SET, lane_count,
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DP_TRAINING_LANE0_SET, lane_count,
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dp->link_train.training_lane);
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if (retval)
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return retval;
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@ -565,7 +565,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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lane_count = dp->link_train.lane_count;
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_LANE0_1_STATUS, 2, link_status);
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DP_LANE0_1_STATUS, 2, link_status);
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if (retval)
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return retval;
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@ -575,12 +575,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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}
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retval = exynos_dp_read_bytes_from_dpcd(dp,
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DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
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DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
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if (retval)
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return retval;
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retval = exynos_dp_read_byte_from_dpcd(dp,
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DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED, &link_align);
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DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
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if (retval)
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return retval;
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@ -622,7 +622,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
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exynos_dp_set_lane_link_training(dp,
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dp->link_train.training_lane[lane], lane);
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retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
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retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
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lane_count, dp->link_train.training_lane);
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return retval;
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@ -637,7 +637,7 @@ static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
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* For DP rev.1.1, Maximum link rate of Main Link lanes
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* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
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*/
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
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exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
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*bandwidth = data;
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}
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@ -650,7 +650,7 @@ static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
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* For DP rev.1.1, Maximum number of Main Link lanes
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* 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
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*/
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exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
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exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
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*lane_count = DPCD_MAX_LANE_COUNT(data);
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}
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@ -822,20 +822,20 @@ static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
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exynos_dp_enable_scrambling(dp);
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exynos_dp_read_byte_from_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DP_TRAINING_PATTERN_SET,
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&data);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
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DP_TRAINING_PATTERN_SET,
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(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
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} else {
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exynos_dp_disable_scrambling(dp);
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exynos_dp_read_byte_from_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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DP_TRAINING_PATTERN_SET,
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&data);
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exynos_dp_write_byte_to_dpcd(dp,
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DPCD_ADDR_TRAINING_PATTERN_SET,
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(u8)(data | DPCD_SCRAMBLING_DISABLED));
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DP_TRAINING_PATTERN_SET,
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(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
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}
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}
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@ -14,6 +14,7 @@
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#define _EXYNOS_DP_CORE_H
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#include <drm/drm_crtc.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/exynos_drm.h>
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#define DP_TIMEOUT_LOOP_COUNT 100
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@ -262,69 +263,17 @@ void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
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#define EDID_EXTENSION_FLAG 0x7e
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#define EDID_CHECKSUM 0x7f
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/* Definition for DPCD Register */
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#define DPCD_ADDR_DPCD_REV 0x0000
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#define DPCD_ADDR_MAX_LINK_RATE 0x0001
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#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
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#define DPCD_ADDR_LINK_BW_SET 0x0100
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#define DPCD_ADDR_LANE_COUNT_SET 0x0101
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#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
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#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
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#define DPCD_ADDR_LANE0_1_STATUS 0x0202
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#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
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#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
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#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
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#define DPCD_ADDR_TEST_REQUEST 0x0218
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#define DPCD_ADDR_TEST_RESPONSE 0x0260
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#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
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#define DPCD_ADDR_SINK_POWER_STATE 0x0600
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/* DPCD_ADDR_MAX_LANE_COUNT */
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/* DP_MAX_LANE_COUNT */
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#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
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#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
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/* DPCD_ADDR_LANE_COUNT_SET */
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#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
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/* DP_LANE_COUNT_SET */
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#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
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/* DPCD_ADDR_TRAINING_PATTERN_SET */
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#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
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#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
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#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
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#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
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#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
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/* DPCD_ADDR_TRAINING_LANE0_SET */
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#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
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/* DP_TRAINING_LANE0_SET */
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#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
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#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
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#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
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#define DPCD_MAX_SWING_REACHED (0x1 << 2)
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#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
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#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
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#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
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/* DPCD_ADDR_LANE0_1_STATUS */
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#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
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#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
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#define DPCD_LANE_CR_DONE (0x1 << 0)
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#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
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DPCD_LANE_CHANNEL_EQ_DONE|\
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DPCD_LANE_SYMBOL_LOCKED)
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/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
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#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
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#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
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#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
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/* DPCD_ADDR_TEST_REQUEST */
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#define DPCD_TEST_EDID_READ (0x1 << 2)
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/* DPCD_ADDR_TEST_RESPONSE */
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#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
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/* DPCD_ADDR_SINK_POWER_STATE */
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#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
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#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
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#endif /* _EXYNOS_DP_CORE_H */
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@ -310,6 +310,8 @@
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_TEST_EDID_CHECKSUM 0x261
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#define DP_TEST_SINK 0x270
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#define DP_TEST_SINK_START (1 << 0)
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