mmc: sdhci high speed support
The SDHCI spec implies that is is incorrect to set a clock frequency above 25 MHz without setting the high speed bit. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
This commit is contained in:
Родитель
7ccd266e67
Коммит
077df88483
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@ -616,6 +616,7 @@ static void sdhci_finish_command(struct sdhci_host *host)
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static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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{
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int div;
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int div;
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u8 ctrl;
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u16 clk;
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u16 clk;
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unsigned long timeout;
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unsigned long timeout;
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@ -624,6 +625,13 @@ static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
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writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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if (clock > 25000000)
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ctrl |= SDHCI_CTRL_HISPD;
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else
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ctrl &= ~SDHCI_CTRL_HISPD;
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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if (clock == 0)
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if (clock == 0)
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goto out;
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goto out;
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@ -1291,6 +1299,13 @@ static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
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else if (caps & SDHCI_CAN_VDD_180)
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else if (caps & SDHCI_CAN_VDD_180)
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mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
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mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
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if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
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printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
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" but no high speed support.\n",
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host->slot_descr);
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mmc->f_max = 25000000;
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}
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if (mmc->ocr_avail == 0) {
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if (mmc->ocr_avail == 0) {
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printk(KERN_ERR "%s: Hardware doesn't report any "
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printk(KERN_ERR "%s: Hardware doesn't report any "
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"support voltages.\n", host->slot_descr);
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"support voltages.\n", host->slot_descr);
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@ -71,6 +71,7 @@
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_ON 0x01
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@ -138,6 +139,7 @@
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_HISPD 0x00200000
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#define SDHCI_CAN_DO_DMA 0x00400000
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#define SDHCI_CAN_DO_DMA 0x00400000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_330 0x01000000
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_300 0x02000000
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