ASoC: Intel: Skylake: Read HIPCT extension before clearing DONE bit
Host clears DONE bit to signal IPC target it has completed the operation. Once this is done, IPC target i.e. DSP may proceed with the next reply, filling registers with new portion of data. Because of this, host should always read all registers prior to clearing DONE and BUSY bits to ensure no desynchronization happens the time in between clearing bits and reading message data (here, extension). Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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9f90af3a99
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078759399f
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@ -313,6 +313,7 @@ static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
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hipcida = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCIDA);
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hipctdr = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDR);
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hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
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/* reply message from dsp */
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if (hipcida & CNL_ADSP_REG_HIPCIDA_DONE) {
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@ -332,7 +333,6 @@ static irqreturn_t cnl_dsp_irq_thread_handler(int irq, void *context)
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/* new message from dsp */
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if (hipctdr & CNL_ADSP_REG_HIPCTDR_BUSY) {
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hipctdd = sst_dsp_shim_read_unlocked(dsp, CNL_ADSP_REG_HIPCTDD);
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header.primary = hipctdr;
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header.extension = hipctdd;
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dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x",
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@ -511,6 +511,7 @@ irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
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hipcie = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCIE);
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hipct = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCT);
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hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
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/* reply message from DSP */
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if (hipcie & SKL_ADSP_REG_HIPCIE_DONE) {
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@ -530,7 +531,6 @@ irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context)
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/* New message from DSP */
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if (hipct & SKL_ADSP_REG_HIPCT_BUSY) {
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hipcte = sst_dsp_shim_read_unlocked(dsp, SKL_ADSP_REG_HIPCTE);
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header.primary = hipct;
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header.extension = hipcte;
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dev_dbg(dsp->dev, "IPC irq: Firmware respond primary:%x\n",
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