Merge branch 'mlx5_dcs' into rdma.git for-next
Leon Romanovsky says: ==================== Add ConnectX DCS offload support This patchset from Lior adds support of DCI stream channel (DCS) support. DCS is an offload to SW load balancing of DC initiator work requests. A single DC QP initiator (DCI) can be connected to only one target at the time and can't start new connection until the previous work request is completed. This limitation causes to delays when the initiator process needs to transfer data to multiple targets at the same time. ==================== * branch 'mlx5_dcs': RDMA/mlx5: Add DCS offload support RDMA/mlx5: Separate DCI QP creation logic net/mlx5: Add DCS caps & fields support
This commit is contained in:
Jason Gunthorpe
Коммит
07d0f314ba
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@ -1174,6 +1174,16 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
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MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
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}
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if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
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resp.response_length += sizeof(resp.dci_streams_caps);
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resp.dci_streams_caps.max_log_num_concurent =
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MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
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resp.dci_streams_caps.max_log_num_errored =
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MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
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}
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if (uhw_outlen) {
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err = ib_copy_to_udata(uhw, &resp, resp.response_length);
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@ -1982,6 +1982,167 @@ static int create_xrc_tgt_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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return 0;
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}
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static int create_dci(struct mlx5_ib_dev *dev, struct ib_pd *pd,
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struct mlx5_ib_qp *qp,
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struct mlx5_create_qp_params *params)
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{
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struct ib_qp_init_attr *init_attr = params->attr;
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struct mlx5_ib_create_qp *ucmd = params->ucmd;
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u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
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struct ib_udata *udata = params->udata;
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u32 uidx = params->uidx;
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struct mlx5_ib_resources *devr = &dev->devr;
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int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
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struct mlx5_core_dev *mdev = dev->mdev;
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struct mlx5_ib_cq *send_cq;
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struct mlx5_ib_cq *recv_cq;
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unsigned long flags;
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struct mlx5_ib_qp_base *base;
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int ts_format;
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int mlx5_st;
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void *qpc;
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u32 *in;
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int err;
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spin_lock_init(&qp->sq.lock);
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spin_lock_init(&qp->rq.lock);
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mlx5_st = to_mlx5_st(qp->type);
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if (mlx5_st < 0)
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return -EINVAL;
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if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
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qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
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base = &qp->trans_qp.base;
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qp->has_rq = qp_has_rq(init_attr);
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err = set_rq_size(dev, &init_attr->cap, qp->has_rq, qp, ucmd);
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if (err) {
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mlx5_ib_dbg(dev, "err %d\n", err);
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return err;
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}
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if (ucmd->rq_wqe_shift != qp->rq.wqe_shift ||
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ucmd->rq_wqe_count != qp->rq.wqe_cnt)
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return -EINVAL;
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if (ucmd->sq_wqe_count > (1 << MLX5_CAP_GEN(mdev, log_max_qp_sz)))
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return -EINVAL;
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ts_format = get_qp_ts_format(dev, to_mcq(init_attr->send_cq),
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to_mcq(init_attr->recv_cq));
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if (ts_format < 0)
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return ts_format;
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err = _create_user_qp(dev, pd, qp, udata, init_attr, &in, ¶ms->resp,
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&inlen, base, ucmd);
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if (err)
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return err;
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if (MLX5_CAP_GEN(mdev, ece_support))
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MLX5_SET(create_qp_in, in, ece, ucmd->ece_options);
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qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
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MLX5_SET(qpc, qpc, st, mlx5_st);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
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MLX5_SET(qpc, qpc, pd, to_mpd(pd)->pdn);
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if (qp->flags_en & MLX5_QP_FLAG_SIGNATURE)
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MLX5_SET(qpc, qpc, wq_signature, 1);
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if (qp->flags & IB_QP_CREATE_CROSS_CHANNEL)
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MLX5_SET(qpc, qpc, cd_master, 1);
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if (qp->flags & IB_QP_CREATE_MANAGED_SEND)
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MLX5_SET(qpc, qpc, cd_slave_send, 1);
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if (qp->flags_en & MLX5_QP_FLAG_SCATTER_CQE)
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configure_requester_scat_cqe(dev, qp, init_attr, qpc);
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if (qp->rq.wqe_cnt) {
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MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
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MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
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}
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if (qp->flags_en & MLX5_QP_FLAG_DCI_STREAM) {
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MLX5_SET(qpc, qpc, log_num_dci_stream_channels,
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ucmd->dci_streams.log_num_concurent);
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MLX5_SET(qpc, qpc, log_num_dci_errored_streams,
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ucmd->dci_streams.log_num_errored);
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}
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MLX5_SET(qpc, qpc, ts_format, ts_format);
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MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
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MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
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/* Set default resources */
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if (init_attr->srq) {
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MLX5_SET(qpc, qpc, xrcd, devr->xrcdn0);
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MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
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to_msrq(init_attr->srq)->msrq.srqn);
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} else {
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MLX5_SET(qpc, qpc, xrcd, devr->xrcdn1);
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MLX5_SET(qpc, qpc, srqn_rmpn_xrqn,
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to_msrq(devr->s1)->msrq.srqn);
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}
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if (init_attr->send_cq)
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MLX5_SET(qpc, qpc, cqn_snd,
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to_mcq(init_attr->send_cq)->mcq.cqn);
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if (init_attr->recv_cq)
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MLX5_SET(qpc, qpc, cqn_rcv,
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to_mcq(init_attr->recv_cq)->mcq.cqn);
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MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
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/* 0xffffff means we ask to work with cqe version 0 */
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if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
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MLX5_SET(qpc, qpc, user_index, uidx);
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if (qp->flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
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MLX5_SET(qpc, qpc, end_padding_mode,
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MLX5_WQ_END_PAD_MODE_ALIGN);
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/* Special case to clean flag */
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qp->flags &= ~IB_QP_CREATE_PCI_WRITE_END_PADDING;
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}
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err = mlx5_qpc_create_qp(dev, &base->mqp, in, inlen, out);
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kvfree(in);
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if (err)
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goto err_create;
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base->container_mibqp = qp;
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base->mqp.event = mlx5_ib_qp_event;
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if (MLX5_CAP_GEN(mdev, ece_support))
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params->resp.ece_options = MLX5_GET(create_qp_out, out, ece);
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get_cqs(qp->type, init_attr->send_cq, init_attr->recv_cq,
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&send_cq, &recv_cq);
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spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
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mlx5_ib_lock_cqs(send_cq, recv_cq);
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/* Maintain device to QPs access, needed for further handling via reset
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* flow
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*/
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list_add_tail(&qp->qps_list, &dev->qp_list);
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/* Maintain CQ to QPs access, needed for further handling via reset flow
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*/
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if (send_cq)
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list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
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if (recv_cq)
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list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
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mlx5_ib_unlock_cqs(send_cq, recv_cq);
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spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
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return 0;
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err_create:
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destroy_qp(dev, qp, base, udata);
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return err;
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}
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static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
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struct mlx5_ib_qp *qp,
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struct mlx5_create_qp_params *params)
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@ -2653,6 +2814,10 @@ static int process_vendor_flags(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCI, true, qp);
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process_vendor_flag(dev, &flags, MLX5_QP_FLAG_TYPE_DCT, true, qp);
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process_vendor_flag(dev, &flags, MLX5_QP_FLAG_DCI_STREAM,
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MLX5_CAP_GEN(mdev, log_max_dci_stream_channels) &&
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MLX5_CAP_GEN(mdev, log_max_dci_errored_streams),
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qp);
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process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SIGNATURE, true, qp);
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process_vendor_flag(dev, &flags, MLX5_QP_FLAG_SCATTER_CQE,
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@ -2848,6 +3013,9 @@ static int create_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
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case MLX5_IB_QPT_DCT:
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err = create_dct(dev, pd, qp, params);
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break;
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case MLX5_IB_QPT_DCI:
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err = create_dci(dev, pd, qp, params);
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break;
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case IB_QPT_XRC_TGT:
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err = create_xrc_tgt_qp(dev, qp, params);
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break;
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@ -1651,7 +1651,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 max_geneve_tlv_option_data_len[0x5];
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u8 reserved_at_570[0x10];
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u8 reserved_at_580[0x33];
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u8 reserved_at_580[0xb];
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u8 log_max_dci_stream_channels[0x5];
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u8 reserved_at_590[0x3];
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u8 log_max_dci_errored_streams[0x5];
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u8 reserved_at_598[0x8];
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u8 reserved_at_5a0[0x13];
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u8 log_max_dek[0x5];
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u8 reserved_at_5b8[0x4];
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u8 mini_cqe_resp_stride_index[0x1];
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@ -3020,10 +3026,12 @@ struct mlx5_ifc_qpc_bits {
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u8 reserved_at_3c0[0x8];
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u8 next_send_psn[0x18];
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u8 reserved_at_3e0[0x8];
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u8 reserved_at_3e0[0x3];
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u8 log_num_dci_stream_channels[0x5];
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u8 cqn_snd[0x18];
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u8 reserved_at_400[0x8];
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u8 reserved_at_400[0x3];
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u8 log_num_dci_errored_streams[0x5];
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u8 deth_sqpn[0x18];
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u8 reserved_at_420[0x20];
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@ -50,6 +50,7 @@ enum {
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MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8,
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MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9,
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MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10,
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MLX5_QP_FLAG_DCI_STREAM = 1 << 11,
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};
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enum {
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@ -238,6 +239,11 @@ struct mlx5_ib_striding_rq_caps {
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__u32 reserved;
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};
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struct mlx5_ib_dci_streams_caps {
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__u8 max_log_num_concurent;
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__u8 max_log_num_errored;
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};
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enum mlx5_ib_query_dev_resp_flags {
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/* Support 128B CQE compression */
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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@ -266,7 +272,8 @@ struct mlx5_ib_query_device_resp {
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struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
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struct mlx5_ib_striding_rq_caps striding_rq_caps;
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__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
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__u32 reserved;
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struct mlx5_ib_dci_streams_caps dci_streams_caps;
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__u16 reserved;
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};
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enum mlx5_ib_create_cq_flags {
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@ -313,6 +320,11 @@ struct mlx5_ib_create_srq_resp {
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__u32 reserved;
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};
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struct mlx5_ib_create_qp_dci_streams {
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__u8 log_num_concurent;
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__u8 log_num_errored;
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};
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struct mlx5_ib_create_qp {
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__aligned_u64 buf_addr;
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__aligned_u64 db_addr;
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@ -327,7 +339,8 @@ struct mlx5_ib_create_qp {
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__aligned_u64 access_key;
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};
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__u32 ece_options;
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__u32 reserved;
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struct mlx5_ib_create_qp_dci_streams dci_streams;
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__u16 reserved;
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};
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/* RX Hash function flags */
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