dt-bindings: Add HDA support for Tegra234
Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -136,4 +136,8 @@
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief 32K input clock provided by PMIC */
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#define TEGRA234_CLK_CLK_32K 289U
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/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
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#define TEGRA234_CLK_AZA_2XBIT 457U
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/** @brief aza_2xbitclk / 2 (aza_bitclk) */
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#define TEGRA234_CLK_AZA_BIT 458U
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#endif
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@ -10,6 +10,7 @@
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/* NISO0 stream IDs */
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#define TEGRA234_SID_APE 0x02
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#define TEGRA234_SID_HDA 0x03
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/* NISO1 stream IDs */
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#define TEGRA234_SID_SDMMC4 0x02
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@ -19,6 +20,10 @@
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* memory client IDs
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*/
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/* High-definition audio (HDA) read clients */
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#define TEGRA234_MEMORY_CLIENT_HDAR 0x15
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/* High-definition audio (HDA) write clients */
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#define TEGRA234_MEMORY_CLIENT_HDAW 0x35
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/* sdmmcd memory read client */
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#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmcd memory write client */
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@ -5,5 +5,6 @@
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#define __ABI_MACH_T234_POWERGATE_T234_H_
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#define TEGRA234_POWER_DOMAIN_AUD 2U
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#define TEGRA234_POWER_DOMAIN_DISP 3U
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#endif
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@ -10,6 +10,8 @@
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* @brief Identifiers for Resets controllable by firmware
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* @{
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*/
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#define TEGRA234_RESET_HDA 20U
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#define TEGRA234_RESET_HDACODEC 21U
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#define TEGRA234_RESET_I2C1 24U
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#define TEGRA234_RESET_I2C2 29U
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#define TEGRA234_RESET_I2C3 30U
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