Documentation: Make fujitsu/frv/kernel-ABI.txt 80 columns wide
Documentation: Make kernel-ABI.txt 80 columns wide Note that this only has line-wrapping and white-space changes. No text was changed at all. Signed-Off-By: Horms <horms@verge.net.au> Signed-off-by: Adrian Bunk <bunk@stusta.de>
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@ -1,17 +1,19 @@
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=================================
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INTERNAL KERNEL ABI FOR FR-V ARCH
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=================================
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=================================
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INTERNAL KERNEL ABI FOR FR-V ARCH
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=================================
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The internal FRV kernel ABI is not quite the same as the userspace ABI. A number of the registers
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are used for special purposed, and the ABI is not consistent between modules vs core, and MMU vs
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no-MMU.
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The internal FRV kernel ABI is not quite the same as the userspace ABI. A
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number of the registers are used for special purposed, and the ABI is not
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consistent between modules vs core, and MMU vs no-MMU.
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This partly stems from the fact that FRV CPUs do not have a separate supervisor stack pointer, and
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most of them do not have any scratch registers, thus requiring at least one general purpose
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register to be clobbered in such an event. Also, within the kernel core, it is possible to simply
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jump or call directly between functions using a relative offset. This cannot be extended to modules
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for the displacement is likely to be too far. Thus in modules the address of a function to call
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must be calculated in a register and then used, requiring two extra instructions.
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This partly stems from the fact that FRV CPUs do not have a separate
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supervisor stack pointer, and most of them do not have any scratch
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registers, thus requiring at least one general purpose register to be
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clobbered in such an event. Also, within the kernel core, it is possible to
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simply jump or call directly between functions using a relative offset.
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This cannot be extended to modules for the displacement is likely to be too
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far. Thus in modules the address of a function to call must be calculated
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in a register and then used, requiring two extra instructions.
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This document has the following sections:
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@ -39,7 +41,8 @@ When a system call is made, the following registers are effective:
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CPU OPERATING MODES
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===================
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The FR-V CPU has three basic operating modes. In order of increasing capability:
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The FR-V CPU has three basic operating modes. In order of increasing
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capability:
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(1) User mode.
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@ -47,42 +50,46 @@ The FR-V CPU has three basic operating modes. In order of increasing capability:
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(2) Kernel mode.
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Normal kernel mode. There are many additional control registers available that may be
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accessed in this mode, in addition to all the stuff available to user mode. This has two
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submodes:
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Normal kernel mode. There are many additional control registers
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available that may be accessed in this mode, in addition to all the
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stuff available to user mode. This has two submodes:
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(a) Exceptions enabled (PSR.T == 1).
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Exceptions will invoke the appropriate normal kernel mode handler. On entry to the
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handler, the PSR.T bit will be cleared.
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Exceptions will invoke the appropriate normal kernel mode
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handler. On entry to the handler, the PSR.T bit will be cleared.
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(b) Exceptions disabled (PSR.T == 0).
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No exceptions or interrupts may happen. Any mandatory exceptions will cause the CPU to
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halt unless the CPU is told to jump into debug mode instead.
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No exceptions or interrupts may happen. Any mandatory exceptions
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will cause the CPU to halt unless the CPU is told to jump into
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debug mode instead.
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(3) Debug mode.
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No exceptions may happen in this mode. Memory protection and management exceptions will be
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flagged for later consideration, but the exception handler won't be invoked. Debugging traps
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such as hardware breakpoints and watchpoints will be ignored. This mode is entered only by
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debugging events obtained from the other two modes.
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No exceptions may happen in this mode. Memory protection and
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management exceptions will be flagged for later consideration, but
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the exception handler won't be invoked. Debugging traps such as
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hardware breakpoints and watchpoints will be ignored. This mode is
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entered only by debugging events obtained from the other two modes.
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All kernel mode registers may be accessed, plus a few extra debugging specific registers.
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All kernel mode registers may be accessed, plus a few extra debugging
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specific registers.
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=================================
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INTERNAL KERNEL-MODE REGISTER ABI
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=================================
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There are a number of permanent register assignments that are set up by entry.S in the exception
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prologue. Note that there is a complete set of exception prologues for each of user->kernel
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transition and kernel->kernel transition. There are also user->debug and kernel->debug mode
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transition prologues.
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There are a number of permanent register assignments that are set up by
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entry.S in the exception prologue. Note that there is a complete set of
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exception prologues for each of user->kernel transition and kernel->kernel
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transition. There are also user->debug and kernel->debug mode transition
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prologues.
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REGISTER FLAVOUR USE
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=============== ======= ====================================================
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=============== ======= ==============================================
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GR1 Supervisor stack pointer
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GR15 Current thread info pointer
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GR16 GP-Rel base register for small data
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@ -92,10 +99,12 @@ transition prologues.
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GR31 NOMMU Destroyed by debug mode entry
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GR31 MMU Destroyed by TLB miss kernel mode entry
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CCR.ICC2 Virtual interrupt disablement tracking
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CCCR.CC3 Cleared by exception prologue (atomic op emulation)
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CCCR.CC3 Cleared by exception prologue
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(atomic op emulation)
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SCR0 MMU See mmu-layout.txt.
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SCR1 MMU See mmu-layout.txt.
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SCR2 MMU Save for EAR0 (destroyed by icache insns in debug mode)
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SCR2 MMU Save for EAR0 (destroyed by icache insns
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in debug mode)
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SCR3 MMU Save for GR31 during debug exceptions
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DAMR/IAMR NOMMU Fixed memory protection layout.
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DAMR/IAMR MMU See mmu-layout.txt.
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@ -104,18 +113,21 @@ transition prologues.
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Certain registers are also used or modified across function calls:
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REGISTER CALL RETURN
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=============== =============================== ===============================
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=============== =============================== ======================
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GR0 Fixed Zero -
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GR2 Function call frame pointer
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GR3 Special Preserved
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GR3-GR7 - Clobbered
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GR8 Function call arg #1 Return value (or clobbered)
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GR9 Function call arg #2 Return value MSW (or clobbered)
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GR8 Function call arg #1 Return value
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(or clobbered)
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GR9 Function call arg #2 Return value MSW
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(or clobbered)
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GR10-GR13 Function call arg #3-#6 Clobbered
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GR14 - Clobbered
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GR15-GR16 Special Preserved
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GR17-GR27 - Preserved
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GR28-GR31 Special Only accessed explicitly
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GR28-GR31 Special Only accessed
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explicitly
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LR Return address after CALL Clobbered
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CCR/CCCR - Mostly Clobbered
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@ -124,46 +136,53 @@ Certain registers are also used or modified across function calls:
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INTERNAL DEBUG-MODE REGISTER ABI
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================================
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This is the same as the kernel-mode register ABI for functions calls. The difference is that in
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debug-mode there's a different stack and a different exception frame. Almost all the global
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registers from kernel-mode (including the stack pointer) may be changed.
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This is the same as the kernel-mode register ABI for functions calls. The
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difference is that in debug-mode there's a different stack and a different
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exception frame. Almost all the global registers from kernel-mode
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(including the stack pointer) may be changed.
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REGISTER FLAVOUR USE
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=============== ======= ====================================================
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=============== ======= ==============================================
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GR1 Debug stack pointer
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GR16 GP-Rel base register for small data
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GR31 Current debug exception frame pointer (__debug_frame)
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GR31 Current debug exception frame pointer
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(__debug_frame)
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SCR3 MMU Saved value of GR31
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Note that debug mode is able to interfere with the kernel's emulated atomic ops, so it must be
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exceedingly careful not to do any that would interact with the main kernel in this regard. Hence
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the debug mode code (gdbstub) is almost completely self-contained. The only external code used is
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the sprintf family of functions.
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Note that debug mode is able to interfere with the kernel's emulated atomic
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ops, so it must be exceedingly careful not to do any that would interact
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with the main kernel in this regard. Hence the debug mode code (gdbstub) is
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almost completely self-contained. The only external code used is the
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sprintf family of functions.
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Futhermore, break.S is so complicated because single-step mode does not switch off on entry to an
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exception. That means unless manually disabled, single-stepping will blithely go on stepping into
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things like interrupts. See gdbstub.txt for more information.
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Futhermore, break.S is so complicated because single-step mode does not
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switch off on entry to an exception. That means unless manually disabled,
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single-stepping will blithely go on stepping into things like interrupts.
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See gdbstub.txt for more information.
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==========================
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VIRTUAL INTERRUPT HANDLING
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==========================
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Because accesses to the PSR is so slow, and to disable interrupts we have to access it twice (once
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to read and once to write), we don't actually disable interrupts at all if we don't have to. What
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we do instead is use the ICC2 condition code flags to note virtual disablement, such that if we
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then do take an interrupt, we note the flag, really disable interrupts, set another flag and resume
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execution at the point the interrupt happened. Setting condition flags as a side effect of an
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arithmetic or logical instruction is really fast. This use of the ICC2 only occurs within the
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Because accesses to the PSR is so slow, and to disable interrupts we have
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to access it twice (once to read and once to write), we don't actually
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disable interrupts at all if we don't have to. What we do instead is use
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the ICC2 condition code flags to note virtual disablement, such that if we
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then do take an interrupt, we note the flag, really disable interrupts, set
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another flag and resume execution at the point the interrupt happened.
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Setting condition flags as a side effect of an arithmetic or logical
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instruction is really fast. This use of the ICC2 only occurs within the
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kernel - it does not affect userspace.
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The flags we use are:
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(*) CCR.ICC2.Z [Zero flag]
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Set to virtually disable interrupts, clear when interrupts are virtually enabled. Can be
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modified by logical instructions without affecting the Carry flag.
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Set to virtually disable interrupts, clear when interrupts are
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virtually enabled. Can be modified by logical instructions without
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affecting the Carry flag.
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(*) CCR.ICC2.C [Carry flag]
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@ -176,8 +195,9 @@ What happens is this:
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ICC2.Z is 0, ICC2.C is 1.
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(2) An interrupt occurs. The exception prologue examines ICC2.Z and determines that nothing needs
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doing. This is done simply with an unlikely BEQ instruction.
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(2) An interrupt occurs. The exception prologue examines ICC2.Z and
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determines that nothing needs doing. This is done simply with an
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unlikely BEQ instruction.
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(3) The interrupts are disabled (local_irq_disable)
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@ -187,48 +207,56 @@ What happens is this:
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ICC2.Z would be set to 0.
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A TIHI #2 instruction (trap #2 if condition HI - Z==0 && C==0) would be used to trap if
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interrupts were now virtually enabled, but physically disabled - which they're not, so the
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trap isn't taken. The kernel would then be back to state (1).
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A TIHI #2 instruction (trap #2 if condition HI - Z==0 && C==0) would
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be used to trap if interrupts were now virtually enabled, but
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physically disabled - which they're not, so the trap isn't taken. The
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kernel would then be back to state (1).
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(5) An interrupt occurs. The exception prologue examines ICC2.Z and determines that the interrupt
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shouldn't actually have happened. It jumps aside, and there disabled interrupts by setting
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PSR.PIL to 14 and then it clears ICC2.C.
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(5) An interrupt occurs. The exception prologue examines ICC2.Z and
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determines that the interrupt shouldn't actually have happened. It
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jumps aside, and there disabled interrupts by setting PSR.PIL to 14
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and then it clears ICC2.C.
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(6) If interrupts were then saved and disabled again (local_irq_save):
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ICC2.Z would be shifted into the save variable and masked off (giving a 1).
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ICC2.Z would be shifted into the save variable and masked off
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(giving a 1).
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ICC2.Z would then be set to 1 (thus unchanged), and ICC2.C would be unaffected (ie: 0).
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ICC2.Z would then be set to 1 (thus unchanged), and ICC2.C would be
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unaffected (ie: 0).
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(7) If interrupts were then restored from state (6) (local_irq_restore):
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ICC2.Z would be set to indicate the result of XOR'ing the saved value (ie: 1) with 1, which
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gives a result of 0 - thus leaving ICC2.Z set.
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ICC2.Z would be set to indicate the result of XOR'ing the saved
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value (ie: 1) with 1, which gives a result of 0 - thus leaving
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ICC2.Z set.
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ICC2.C would remain unaffected (ie: 0).
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A TIHI #2 instruction would be used to again assay the current state, but this would do
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nothing as Z==1.
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A TIHI #2 instruction would be used to again assay the current state,
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but this would do nothing as Z==1.
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(8) If interrupts were then enabled (local_irq_enable):
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ICC2.Z would be cleared. ICC2.C would be left unaffected. Both flags would now be 0.
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ICC2.Z would be cleared. ICC2.C would be left unaffected. Both
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flags would now be 0.
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A TIHI #2 instruction again issued to assay the current state would then trap as both Z==0
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[interrupts virtually enabled] and C==0 [interrupts really disabled] would then be true.
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A TIHI #2 instruction again issued to assay the current state would
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then trap as both Z==0 [interrupts virtually enabled] and C==0
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[interrupts really disabled] would then be true.
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(9) The trap #2 handler would simply enable hardware interrupts (set PSR.PIL to 0), set ICC2.C to
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1 and return.
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(9) The trap #2 handler would simply enable hardware interrupts
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(set PSR.PIL to 0), set ICC2.C to 1 and return.
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(10) Immediately upon returning, the pending interrupt would be taken.
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(11) The interrupt handler would take the path of actually processing the interrupt (ICC2.Z is
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clear, BEQ fails as per step (2)).
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(11) The interrupt handler would take the path of actually processing the
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interrupt (ICC2.Z is clear, BEQ fails as per step (2)).
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(12) The interrupt handler would then set ICC2.C to 1 since hardware interrupts are definitely
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enabled - or else the kernel wouldn't be here.
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(12) The interrupt handler would then set ICC2.C to 1 since hardware
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interrupts are definitely enabled - or else the kernel wouldn't be here.
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(13) On return from the interrupt handler, things would be back to state (1).
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This trap (#2) is only available in kernel mode. In user mode it will result in SIGILL.
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This trap (#2) is only available in kernel mode. In user mode it will
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result in SIGILL.
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