[SCSI] lpfc 8.3.19: Add latest SLI4 Hardware initialization support
- Add the Lancer FC and FCoE PCI IDs - Add new SLI4 INTF register definitions - Implement new SLI4 doorbell register Signed-off-by: Alex Iannicelli <alex.iannicelli@emulex.com> Signed-off-by: James Smart <james.smart@emulex.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
James Smart
James Bottomley
Родитель
63e801ce68
Коммит
085c647c33
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@ -1172,7 +1172,10 @@ typedef struct {
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#define PCI_VENDOR_ID_EMULEX 0x10df
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#define PCI_DEVICE_ID_FIREFLY 0x1ae5
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#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
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#define PCI_DEVICE_ID_BALIUS 0xe131
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#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
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#define PCI_DEVICE_ID_LANCER_FC 0xe200
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#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
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#define PCI_DEVICE_ID_SAT_SMB 0xf011
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#define PCI_DEVICE_ID_SAT_MID 0xf015
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#define PCI_DEVICE_ID_RFLY 0xf095
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@ -1189,6 +1192,7 @@ typedef struct {
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#define PCI_DEVICE_ID_SAT 0xf100
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#define PCI_DEVICE_ID_SAT_SCSP 0xf111
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#define PCI_DEVICE_ID_SAT_DCSP 0xf112
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#define PCI_DEVICE_ID_FALCON 0xf180
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#define PCI_DEVICE_ID_SUPERFLY 0xf700
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#define PCI_DEVICE_ID_DRAGONFLY 0xf800
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#define PCI_DEVICE_ID_CENTAUR 0xf900
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@ -1210,8 +1214,6 @@ typedef struct {
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#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
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#define PCI_DEVICE_ID_TIGERSHARK 0x0704
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#define PCI_DEVICE_ID_TOMCAT 0x0714
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#define PCI_DEVICE_ID_FALCON 0xf180
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#define PCI_DEVICE_ID_BALIUS 0xe131
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#define JEDEC_ID_ADDRESS 0x0080001c
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#define FIREFLY_JEDEC_ID 0x1ACC
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@ -64,29 +64,39 @@ struct lpfc_sli_intf {
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#define lpfc_sli_intf_valid_MASK 0x00000007
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#define lpfc_sli_intf_valid_WORD word0
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#define LPFC_SLI_INTF_VALID 6
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#define lpfc_sli_intf_featurelevel2_SHIFT 24
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#define lpfc_sli_intf_featurelevel2_MASK 0x0000001F
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#define lpfc_sli_intf_featurelevel2_WORD word0
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#define lpfc_sli_intf_featurelevel1_SHIFT 16
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#define lpfc_sli_intf_featurelevel1_MASK 0x000000FF
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#define lpfc_sli_intf_featurelevel1_WORD word0
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#define LPFC_SLI_INTF_FEATURELEVEL1_1 1
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#define LPFC_SLI_INTF_FEATURELEVEL1_2 2
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#define lpfc_sli_intf_sli_hint2_SHIFT 24
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#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
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#define lpfc_sli_intf_sli_hint2_WORD word0
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#define LPFC_SLI_INTF_SLI_HINT2_NONE 0
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#define lpfc_sli_intf_sli_hint1_SHIFT 16
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#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
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#define lpfc_sli_intf_sli_hint1_WORD word0
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#define LPFC_SLI_INTF_SLI_HINT1_NONE 0
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#define LPFC_SLI_INTF_SLI_HINT1_1 1
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#define LPFC_SLI_INTF_SLI_HINT1_2 2
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#define lpfc_sli_intf_if_type_SHIFT 12
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#define lpfc_sli_intf_if_type_MASK 0x0000000F
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#define lpfc_sli_intf_if_type_WORD word0
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#define LPFC_SLI_INTF_IF_TYPE_0 0
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#define LPFC_SLI_INTF_IF_TYPE_1 1
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#define LPFC_SLI_INTF_IF_TYPE_2 2
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#define lpfc_sli_intf_sli_family_SHIFT 8
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#define lpfc_sli_intf_sli_family_MASK 0x000000FF
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#define lpfc_sli_intf_sli_family_MASK 0x0000000F
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#define lpfc_sli_intf_sli_family_WORD word0
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#define LPFC_SLI_INTF_FAMILY_BE2 0
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#define LPFC_SLI_INTF_FAMILY_BE3 1
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#define LPFC_SLI_INTF_FAMILY_BE2 0x0
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#define LPFC_SLI_INTF_FAMILY_BE3 0x1
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#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
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#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
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#define lpfc_sli_intf_slirev_SHIFT 4
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#define lpfc_sli_intf_slirev_MASK 0x0000000F
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#define lpfc_sli_intf_slirev_WORD word0
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#define LPFC_SLI_INTF_REV_SLI3 3
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#define LPFC_SLI_INTF_REV_SLI4 4
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#define lpfc_sli_intf_if_type_SHIFT 0
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#define lpfc_sli_intf_if_type_MASK 0x00000007
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#define lpfc_sli_intf_if_type_WORD word0
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#define LPFC_SLI_INTF_IF_TYPE_0 0
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#define LPFC_SLI_INTF_IF_TYPE_1 1
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#define lpfc_sli_intf_func_type_SHIFT 0
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#define lpfc_sli_intf_func_type_MASK 0x00000001
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#define lpfc_sli_intf_func_type_WORD word0
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#define LPFC_SLI_INTF_IF_TYPE_PHYS 0
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#define LPFC_SLI_INTF_IF_TYPE_VIRT 1
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};
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#define LPFC_SLI4_MBX_EMBED true
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@ -450,13 +460,15 @@ struct lpfc_register {
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uint32_t word0;
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};
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/* The SLI4 INTF register offset is common to all if_type values. */
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#define LPFC_SLI_INTF 0x0058
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/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
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#define LPFC_UERR_STATUS_HI 0x00A4
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#define LPFC_UERR_STATUS_LO 0x00A0
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#define LPFC_UE_MASK_HI 0x00AC
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#define LPFC_UE_MASK_LO 0x00A8
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#define LPFC_SLI_INTF 0x0058
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/* BAR0 Registers */
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#define LPFC_HST_STATE 0x00AC
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#define lpfc_hst_state_perr_SHIFT 31
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#define lpfc_hst_state_perr_MASK 0x1
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@ -480,6 +492,10 @@ struct lpfc_register {
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#define lpfc_hst_state_port_status_MASK 0xFFFF
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#define lpfc_hst_state_port_status_WORD word0
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/*
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* The following Port Status Values apply to SLI4, if_type 0 and 2
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* UCNAs.
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*/
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#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
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#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
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#define LPFC_POST_STAGE_HOST_RDY 0x0002
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@ -514,6 +530,64 @@ struct lpfc_register {
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#define LPFC_POST_STAGE_ARMFW_READY 0xC000
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#define LPFC_POST_STAGE_ARMFW_UE 0xF000
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/* The following BAR0 register sets are defined for if_type 2 UCNAs. */
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#define LPFC_SLIPORT_SEMAPHORE 0x0400
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#define lpfc_sliport_smphr_perr_SHIFT 31
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#define lpfc_sliport_smphr_perr_MASK 0x1
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#define lpfc_sliport_smphr_perr_WORD word0
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#define lpfc_sliport_smphr_sfi_SHIFT 30
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#define lpfc_sliport_smphr_sfi_MASK 0x1
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#define lpfc_sliport_smphr_sfi_WORD word0
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#define lpfc_sliport_smphr_nip_SHIFT 29
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#define lpfc_sliport_smphr_nip_MASK 0x1
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#define lpfc_sliport_smphr_nip_WORD word0
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#define lpfc_sliport_smphr_ipc_SHIFT 28
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#define lpfc_sliport_smphr_ipc_MASK 0x1
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#define lpfc_sliport_smphr_ipc_WORD word0
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#define lpfc_sliport_smphr_scr1_SHIFT 27
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#define lpfc_sliport_smphr_scr1_MASK 0x1
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#define lpfc_sliport_smphr_scr1_WORD word0
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#define lpfc_sliport_smphr_scr2_SHIFT 26
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#define lpfc_sliport_smphr_scr2_MASK 0x1
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#define lpfc_sliport_smphr_scr2_WORD word0
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#define lpfc_sliport_smphr_host_scratch_SHIFT 16
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#define lpfc_sliport_smphr_host_scratch_MASK 0xFF
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#define lpfc_sliport_smphr_host_scratch_WORD word0
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#define lpfc_sliport_smphr_port_status_SHIFT 0
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#define lpfc_sliport_smphr_port_status_MASK 0xFFFF
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#define lpfc_sliport_smphr_port_status_WORD word0
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#define LPFC_SLIPORT_STATUS 0x0404
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#define lpfc_sliport_status_err_SHIFT 31
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#define lpfc_sliport_status_err_MASK 0x1
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#define lpfc_sliport_status_err_WORD word0
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#define lpfc_sliport_status_end_SHIFT 30
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#define lpfc_sliport_status_end_MASK 0x1
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#define lpfc_sliport_status_end_WORD word0
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#define lpfc_sliport_status_oti_SHIFT 29
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#define lpfc_sliport_status_oti_MASK 0x1
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#define lpfc_sliport_status_oti_WORD word0
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#define lpfc_sliport_status_rn_SHIFT 24
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#define lpfc_sliport_status_rn_MASK 0x1
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#define lpfc_sliport_status_rn_WORD word0
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#define lpfc_sliport_status_rdy_SHIFT 23
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#define lpfc_sliport_status_rdy_MASK 0x1
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#define lpfc_sliport_status_rdy_WORD word0
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#define LPFC_SLIPORT_CONTROL 0x0408
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#define lpfc_sliport_ctrl_end_SHIFT 30
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#define lpfc_sliport_ctrl_end_MASK 0x1
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#define lpfc_sliport_ctrl_end_WORD word0
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#define LPFC_SLIPORT_LITTLE_ENDIAN 0
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#define LPFC_SLIPORT_BIG_ENDIAN 1
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#define lpfc_sliport_ctrl_ip_SHIFT 27
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#define lpfc_sliport_ctrl_ip_MASK 0x1
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#define lpfc_sliport_ctrl_ip_WORD word0
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#define LPFC_SLIPORT_ERROR_1 0x040C
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#define LPFC_SLIPORT_ERROR_2 0x0410
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/* BAR1 Registers */
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#define LPFC_IMR_MASK_ALL 0xFFFFFFFF
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#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
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@ -569,14 +643,21 @@ struct lpfc_register {
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#define LPFC_SLI4_INTR30 BIT30
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#define LPFC_SLI4_INTR31 BIT31
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/* BAR2 Registers */
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/*
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* The Doorbell registers defined here exist in different BAR
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* register sets depending on the UCNA Port's reported if_type
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* value. For UCNA ports running SLI4 and if_type 0, they reside in
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* BAR2. For UCNA ports running SLI4 and if_type 2, they reside in
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* BAR0. The offsets are the same so the driver must account for
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* any base address difference.
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*/
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#define LPFC_RQ_DOORBELL 0x00A0
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#define lpfc_rq_doorbell_num_posted_SHIFT 16
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#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
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#define lpfc_rq_doorbell_num_posted_WORD word0
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#define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */
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#define lpfc_rq_doorbell_id_SHIFT 0
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#define lpfc_rq_doorbell_id_MASK 0x03FF
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#define lpfc_rq_doorbell_id_MASK 0xFFFF
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#define lpfc_rq_doorbell_id_WORD word0
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#define LPFC_WQ_DOORBELL 0x0040
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@ -591,6 +672,11 @@ struct lpfc_register {
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#define lpfc_wq_doorbell_id_WORD word0
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#define LPFC_EQCQ_DOORBELL 0x0120
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#define lpfc_eqcq_doorbell_se_SHIFT 31
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#define lpfc_eqcq_doorbell_se_MASK 0x0001
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#define lpfc_eqcq_doorbell_se_WORD word0
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#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
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#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
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#define lpfc_eqcq_doorbell_arm_SHIFT 29
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#define lpfc_eqcq_doorbell_arm_MASK 0x0001
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#define lpfc_eqcq_doorbell_arm_WORD word0
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@ -628,7 +714,7 @@ struct lpfc_register {
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#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
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#define lpfc_mq_doorbell_num_posted_WORD word0
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#define lpfc_mq_doorbell_id_SHIFT 0
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#define lpfc_mq_doorbell_id_MASK 0x03FF
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#define lpfc_mq_doorbell_id_MASK 0xFFFF
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#define lpfc_mq_doorbell_id_WORD word0
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struct lpfc_sli4_cfg_mhdr {
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@ -1853,6 +1853,14 @@ lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
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m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
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"Fibre Channel Adapter"};
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break;
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case PCI_DEVICE_ID_LANCER_FC:
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oneConnect = 1;
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m = (typeof(m)){"Undefined", "PCIe", "Fibre Channel Adapter"};
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break;
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case PCI_DEVICE_ID_LANCER_FCOE:
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oneConnect = 1;
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m = (typeof(m)){"Undefined", "PCIe", "FCoE"};
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break;
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default:
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m = (typeof(m)){"Unknown", "", ""};
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break;
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@ -3950,7 +3958,7 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
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int rc, i, hbq_count, buf_size, dma_buf_size, max_buf_size;
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uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
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struct lpfc_mqe *mqe;
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int longs;
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int longs, sli_family;
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/* Before proceed, wait for POST done and device ready */
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rc = lpfc_sli4_post_status_check(phba);
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@ -4012,12 +4020,22 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
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*/
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buf_size = (sizeof(struct fcp_cmnd) + sizeof(struct fcp_rsp) +
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((phba->cfg_sg_seg_cnt + 2) * sizeof(struct sli4_sge)));
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/* Feature Level 1 hardware is limited to 2 pages */
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if ((bf_get(lpfc_sli_intf_featurelevel1, &phba->sli4_hba.sli_intf) ==
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LPFC_SLI_INTF_FEATURELEVEL1_1))
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max_buf_size = LPFC_SLI4_FL1_MAX_BUF_SIZE;
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else
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max_buf_size = LPFC_SLI4_MAX_BUF_SIZE;
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sli_family = bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf);
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max_buf_size = LPFC_SLI4_MAX_BUF_SIZE;
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switch (sli_family) {
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case LPFC_SLI_INTF_FAMILY_BE2:
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case LPFC_SLI_INTF_FAMILY_BE3:
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/* There is a single hint for BE - 2 pages per BPL. */
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if (bf_get(lpfc_sli_intf_sli_hint1, &phba->sli4_hba.sli_intf) ==
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LPFC_SLI_INTF_SLI_HINT1_1)
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max_buf_size = LPFC_SLI4_FL1_MAX_BUF_SIZE;
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break;
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case LPFC_SLI_INTF_FAMILY_LNCR_A0:
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case LPFC_SLI_INTF_FAMILY_LNCR_B0:
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default:
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break;
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}
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for (dma_buf_size = LPFC_SLI4_MIN_BUF_SIZE;
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dma_buf_size < max_buf_size && buf_size > dma_buf_size;
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dma_buf_size = dma_buf_size << 1)
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@ -5233,16 +5251,22 @@ lpfc_sli4_post_status_check(struct lpfc_hba *phba)
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&phba->sli4_hba.sli_intf) == LPFC_SLI_INTF_VALID) {
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lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
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"2534 Device Info: ChipType=0x%x, SliRev=0x%x, "
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"FeatureL1=0x%x, FeatureL2=0x%x\n",
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"IFType=0x%x, SLIHint_1=0x%x, SLIHint_2=0x%x, "
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"FT=0x%x\n",
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bf_get(lpfc_sli_intf_sli_family,
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&phba->sli4_hba.sli_intf),
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bf_get(lpfc_sli_intf_slirev,
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&phba->sli4_hba.sli_intf),
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bf_get(lpfc_sli_intf_featurelevel1,
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bf_get(lpfc_sli_intf_if_type,
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&phba->sli4_hba.sli_intf),
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bf_get(lpfc_sli_intf_featurelevel2,
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bf_get(lpfc_sli_intf_sli_hint1,
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&phba->sli4_hba.sli_intf),
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bf_get(lpfc_sli_intf_sli_hint2,
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&phba->sli4_hba.sli_intf),
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bf_get(lpfc_sli_intf_func_type,
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&phba->sli4_hba.sli_intf));
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}
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phba->sli4_hba.ue_mask_lo = readl(phba->sli4_hba.UEMASKLOregaddr);
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phba->sli4_hba.ue_mask_hi = readl(phba->sli4_hba.UEMASKHIregaddr);
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/* With uncoverable error, log the error message and return error */
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@ -8992,6 +9016,10 @@ static struct pci_device_id lpfc_id_table[] = {
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PCI_ANY_ID, PCI_ANY_ID, },
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{PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_BALIUS,
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PCI_ANY_ID, PCI_ANY_ID, },
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{PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC,
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PCI_ANY_ID, PCI_ANY_ID, },
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{PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FCOE,
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PCI_ANY_ID, PCI_ANY_ID, },
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{ 0 }
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};
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