PCI: Add support for PASID capability
Devices supporting Process Address Space Identifiers (PASIDs) can use an IOMMU to access multiple IO address spaces at the same time. A PCIe device indicates support for this feature by implementing the PASID capability. This patch adds support for the capability to the Linux kernel. Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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c320b976d7
Коммит
086ac11f64
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@ -94,6 +94,19 @@ config PCI_PRI
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If unsure, say N.
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If unsure, say N.
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config PCI_PASID
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bool "PCI PASID support"
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depends on PCI
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select PCI_ATS
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help
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Process Address Space Identifiers (PASIDs) can be used by PCI devices
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to access more than one IO address space at the same time. To make
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use of this feature an IOMMU is required which also supports PASIDs.
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Select this option if you have such an IOMMU and want to compile the
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driver for it into your kernel.
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If unsure, say N.
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config PCI_IOAPIC
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config PCI_IOAPIC
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bool
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bool
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depends on PCI
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depends on PCI
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@ -7,6 +7,7 @@
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* PCI Express I/O Virtualization (IOV) support.
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* PCI Express I/O Virtualization (IOV) support.
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* Address Translation Service 1.0
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* Address Translation Service 1.0
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* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
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* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
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* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
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*/
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*/
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#include <linux/pci-ats.h>
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#include <linux/pci-ats.h>
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@ -323,3 +324,115 @@ int pci_pri_status(struct pci_dev *pdev)
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}
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}
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EXPORT_SYMBOL_GPL(pci_pri_status);
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EXPORT_SYMBOL_GPL(pci_pri_status);
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#endif /* CONFIG_PCI_PRI */
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#endif /* CONFIG_PCI_PRI */
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#ifdef CONFIG_PCI_PASID
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/**
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* pci_enable_pasid - Enable the PASID capability
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* @pdev: PCI device structure
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* @features: Features to enable
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*
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* Returns 0 on success, negative value on error. This function checks
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* whether the features are actually supported by the device and returns
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* an error if not.
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*/
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int pci_enable_pasid(struct pci_dev *pdev, int features)
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{
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u16 control, supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);
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pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
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if (!(supported & PCI_PASID_ENABLE))
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return -EINVAL;
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supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;
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/* User wants to enable anything unsupported? */
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if ((supported & features) != features)
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return -EINVAL;
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control = PCI_PASID_ENABLE | features;
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pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_pasid);
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/**
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* pci_disable_pasid - Disable the PASID capability
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* @pdev: PCI device structure
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*
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*/
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void pci_disable_pasid(struct pci_dev *pdev)
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{
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u16 control = 0;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
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if (!pos)
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return;
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pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);
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}
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EXPORT_SYMBOL_GPL(pci_disable_pasid);
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/**
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* pci_pasid_features - Check which PASID features are supported
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* @pdev: PCI device structure
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*
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* Returns a negative value when no PASI capability is present.
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* Otherwise is returns a bitmask with supported features. Current
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* features reported are:
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* PCI_PASID_ENABLE - PASID capability can be enabled
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* PCI_PASID_EXEC - Execute permission supported
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* PCI_PASID_PRIV - Priviledged mode supported
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*/
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int pci_pasid_features(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
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supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV;
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return supported;
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}
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EXPORT_SYMBOL_GPL(pci_pasid_features);
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#define PASID_NUMBER_SHIFT 8
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#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
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/**
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* pci_max_pasid - Get maximum number of PASIDs supported by device
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* @pdev: PCI device structure
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*
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* Returns negative value when PASID capability is not present.
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* Otherwise it returns the numer of supported PASIDs.
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*/
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int pci_max_pasids(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);
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supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
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return (1 << supported);
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}
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EXPORT_SYMBOL_GPL(pci_max_pasids);
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#endif /* CONFIG_PCI_PASID */
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@ -93,4 +93,35 @@ static inline int pci_pri_status(struct pci_dev *pdev)
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}
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}
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#endif /* CONFIG_PCI_PRI */
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#endif /* CONFIG_PCI_PRI */
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#ifdef CONFIG_PCI_PASID
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extern int pci_enable_pasid(struct pci_dev *pdev, int features);
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extern void pci_disable_pasid(struct pci_dev *pdev);
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extern int pci_pasid_features(struct pci_dev *pdev);
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extern int pci_max_pasids(struct pci_dev *pdev);
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#else /* CONFIG_PCI_PASID */
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static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
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{
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return -EINVAL;
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}
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static inline void pci_disable_pasid(struct pci_dev *pdev)
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{
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}
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static inline int pci_pasid_features(struct pci_dev *pdev)
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{
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return -EINVAL;
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}
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static inline int pci_max_pasids(struct pci_dev *pdev)
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{
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return -EINVAL;
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}
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#endif /* CONFIG_PCI_PASID */
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#endif /* LINUX_PCI_ATS_H*/
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#endif /* LINUX_PCI_ATS_H*/
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@ -675,6 +675,14 @@
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#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */
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#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */
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#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */
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#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */
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/* PASID capability */
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#define PCI_PASID_CAP 0x1b /* PASID capability ID */
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#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */
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#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */
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#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */
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#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */
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#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */
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/* Single Root I/O Virtualization */
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/* Single Root I/O Virtualization */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
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#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
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