x86 and PPC bugfixes, mostly introduced in 4.19-rc1.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJbtxXyAAoJEL/70l94x66D52kH/jEbBo/jz9Jx2bnbxYkG1YzO cIpIRjbRcOKVFNGxjStlJ0PedQBWAfPQl+SywRfqwiSlOOt/yo0lZ5ZewENR2TxO CLQC/OnV/5SU7BJvbsKgH9tc+Wp9X55wBUEalfcvG/knFlmR+eK/7TwTS+hv/U21 uYKRnGfz5AGfdmB9FyCn0blkPNnFaQ8KB+y+INZTkB+YZzNsybow230FRPs22fjX HGeJ7gngah50M5gxDW+YPPNXFhs36x2hsyQXBN9TPxLPHoxTsRRoeqx2nl/UvA+e LXZWg8/UAzXFO/fKVHkJX4jSnCDr2W7HYGNyLPtXFPWhcOelP1h9uHrfuX+fxA4= =UNUo -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Paolo writes: "KVM changes for 4.19-rc7 x86 and PPC bugfixes, mostly introduced in 4.19-rc1." * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: kvm: nVMX: fix entry with pending interrupt if APICv is enabled KVM: VMX: hide flexpriority from guest when disabled at the module level KVM: VMX: check for existence of secondary exec controls before accessing KVM: PPC: Book3S HV: Avoid crash from THP collapse during radix page fault KVM: x86: fix L1TF's MMIO GFN calculation tools/kvm_stat: cut down decimal places in update interval dialog KVM: nVMX: Fix emulation of VM_ENTRY_LOAD_BNDCFGS KVM: x86: Do not use kvm_x86_ops->mpx_supported() directly KVM: nVMX: Do not expose MPX VMX controls when guest MPX disabled KVM: x86: never trap MSR_KERNEL_GS_BASE
This commit is contained in:
Greg Kroah-Hartman
Коммит
08b297bb10
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@ -646,6 +646,16 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
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*/
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local_irq_disable();
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ptep = __find_linux_pte(vcpu->arch.pgdir, hva, NULL, &shift);
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/*
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* If the PTE disappeared temporarily due to a THP
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* collapse, just return and let the guest try again.
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*/
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if (!ptep) {
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local_irq_enable();
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if (page)
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put_page(page);
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return RESUME_GUEST;
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}
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pte = *ptep;
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local_irq_enable();
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@ -249,6 +249,17 @@ static u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
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*/
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static const u64 shadow_nonpresent_or_rsvd_mask_len = 5;
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/*
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* In some cases, we need to preserve the GFN of a non-present or reserved
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* SPTE when we usurp the upper five bits of the physical address space to
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* defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
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* shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
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* left into the reserved bits, i.e. the GFN in the SPTE will be split into
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* high and low parts. This mask covers the lower bits of the GFN.
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*/
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static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
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static void mmu_spte_set(u64 *sptep, u64 spte);
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static union kvm_mmu_page_role
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kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
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@ -357,9 +368,7 @@ static bool is_mmio_spte(u64 spte)
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static gfn_t get_mmio_spte_gfn(u64 spte)
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{
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u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask |
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shadow_nonpresent_or_rsvd_mask;
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u64 gpa = spte & ~mask;
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u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
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gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len)
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& shadow_nonpresent_or_rsvd_mask;
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@ -423,6 +432,8 @@ EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
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static void kvm_mmu_reset_all_pte_masks(void)
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{
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u8 low_phys_bits;
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shadow_user_mask = 0;
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shadow_accessed_mask = 0;
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shadow_dirty_mask = 0;
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@ -437,12 +448,17 @@ static void kvm_mmu_reset_all_pte_masks(void)
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* appropriate mask to guard against L1TF attacks. Otherwise, it is
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* assumed that the CPU is not vulnerable to L1TF.
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*/
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low_phys_bits = boot_cpu_data.x86_phys_bits;
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if (boot_cpu_data.x86_phys_bits <
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52 - shadow_nonpresent_or_rsvd_mask_len)
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52 - shadow_nonpresent_or_rsvd_mask_len) {
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shadow_nonpresent_or_rsvd_mask =
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rsvd_bits(boot_cpu_data.x86_phys_bits -
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shadow_nonpresent_or_rsvd_mask_len,
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boot_cpu_data.x86_phys_bits - 1);
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low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len;
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}
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shadow_nonpresent_or_rsvd_lower_gfn_mask =
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GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);
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}
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static int is_cpuid_PSE36(void)
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@ -121,7 +121,6 @@ module_param_named(pml, enable_pml, bool, S_IRUGO);
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#define MSR_BITMAP_MODE_X2APIC 1
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#define MSR_BITMAP_MODE_X2APIC_APICV 2
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#define MSR_BITMAP_MODE_LM 4
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#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
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@ -857,6 +856,7 @@ struct nested_vmx {
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/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
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u64 vmcs01_debugctl;
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u64 vmcs01_guest_bndcfgs;
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u16 vpid02;
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u16 last_vpid;
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@ -2899,8 +2899,7 @@ static void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
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vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
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}
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if (is_long_mode(&vmx->vcpu))
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wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
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#else
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savesegment(fs, fs_sel);
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savesegment(gs, gs_sel);
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@ -2951,8 +2950,7 @@ static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
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vmx->loaded_cpu_state = NULL;
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#ifdef CONFIG_X86_64
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if (is_long_mode(&vmx->vcpu))
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rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
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#endif
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if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
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kvm_load_ldt(host_state->ldt_sel);
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@ -2980,24 +2978,19 @@ static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
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#ifdef CONFIG_X86_64
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static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
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{
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if (is_long_mode(&vmx->vcpu)) {
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preempt_disable();
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if (vmx->loaded_cpu_state)
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rdmsrl(MSR_KERNEL_GS_BASE,
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vmx->msr_guest_kernel_gs_base);
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preempt_enable();
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}
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preempt_disable();
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if (vmx->loaded_cpu_state)
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rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
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preempt_enable();
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return vmx->msr_guest_kernel_gs_base;
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}
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static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
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{
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if (is_long_mode(&vmx->vcpu)) {
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preempt_disable();
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if (vmx->loaded_cpu_state)
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wrmsrl(MSR_KERNEL_GS_BASE, data);
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preempt_enable();
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}
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preempt_disable();
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if (vmx->loaded_cpu_state)
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wrmsrl(MSR_KERNEL_GS_BASE, data);
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preempt_enable();
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vmx->msr_guest_kernel_gs_base = data;
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}
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#endif
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@ -3533,9 +3526,6 @@ static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
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VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
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VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
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if (kvm_mpx_supported())
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msrs->exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
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/* We support free control of debug control saving. */
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msrs->exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
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@ -3552,8 +3542,6 @@ static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
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VM_ENTRY_LOAD_IA32_PAT;
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msrs->entry_ctls_high |=
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(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
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if (kvm_mpx_supported())
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msrs->entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
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/* We support free control of debug control loading. */
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msrs->entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
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@ -3601,12 +3589,12 @@ static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
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msrs->secondary_ctls_high);
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msrs->secondary_ctls_low = 0;
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msrs->secondary_ctls_high &=
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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SECONDARY_EXEC_DESC |
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SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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SECONDARY_EXEC_APIC_REGISTER_VIRT |
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
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SECONDARY_EXEC_WBINVD_EXITING;
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/*
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* We can emulate "VMCS shadowing," even if the hardware
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* doesn't support it.
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@ -3663,6 +3651,10 @@ static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, bool apicv)
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msrs->secondary_ctls_high |=
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SECONDARY_EXEC_UNRESTRICTED_GUEST;
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if (flexpriority_enabled)
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msrs->secondary_ctls_high |=
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
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/* miscellaneous data */
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rdmsr(MSR_IA32_VMX_MISC,
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msrs->misc_low,
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@ -5073,19 +5065,6 @@ static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
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if (!msr)
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return;
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/*
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* MSR_KERNEL_GS_BASE is not intercepted when the guest is in
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* 64-bit mode as a 64-bit kernel may frequently access the
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* MSR. This means we need to manually save/restore the MSR
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* when switching between guest and host state, but only if
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* the guest is in 64-bit mode. Sync our cached value if the
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* guest is transitioning to 32-bit mode and the CPU contains
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* guest state, i.e. the cache is stale.
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*/
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#ifdef CONFIG_X86_64
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if (!(efer & EFER_LMA))
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(void)vmx_read_guest_kernel_gs_base(vmx);
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#endif
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vcpu->arch.efer = efer;
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if (efer & EFER_LMA) {
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vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
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@ -6078,9 +6057,6 @@ static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
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mode |= MSR_BITMAP_MODE_X2APIC_APICV;
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}
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if (is_long_mode(vcpu))
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mode |= MSR_BITMAP_MODE_LM;
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return mode;
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}
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@ -6121,9 +6097,6 @@ static void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
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if (!changed)
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return;
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vmx_set_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW,
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!(mode & MSR_BITMAP_MODE_LM));
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if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
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vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
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@ -6189,6 +6162,11 @@ static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
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nested_mark_vmcs12_pages_dirty(vcpu);
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}
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static u8 vmx_get_rvi(void)
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{
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return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
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}
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static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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@ -6201,7 +6179,7 @@ static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
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WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
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return false;
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rvi = vmcs_read16(GUEST_INTR_STATUS) & 0xff;
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rvi = vmx_get_rvi();
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vapic_page = kmap(vmx->nested.virtual_apic_page);
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vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
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@ -10245,15 +10223,16 @@ static void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
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if (!lapic_in_kernel(vcpu))
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return;
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if (!flexpriority_enabled &&
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!cpu_has_vmx_virtualize_x2apic_mode())
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return;
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/* Postpone execution until vmcs01 is the current VMCS. */
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if (is_guest_mode(vcpu)) {
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to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
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return;
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}
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if (!cpu_need_tpr_shadow(vcpu))
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return;
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sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
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sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
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@ -10375,6 +10354,14 @@ static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
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return max_irr;
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}
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static u8 vmx_has_apicv_interrupt(struct kvm_vcpu *vcpu)
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{
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u8 rvi = vmx_get_rvi();
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u8 vppr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_PROCPRI);
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return ((rvi & 0xf0) > (vppr & 0xf0));
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}
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static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
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{
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if (!kvm_vcpu_apicv_active(vcpu))
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@ -11264,6 +11251,23 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
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#undef cr4_fixed1_update
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}
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static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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if (kvm_mpx_supported()) {
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bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
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if (mpx_enabled) {
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vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
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vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
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} else {
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vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
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vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
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}
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}
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}
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static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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@ -11280,8 +11284,10 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
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to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
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~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
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if (nested_vmx_allowed(vcpu))
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if (nested_vmx_allowed(vcpu)) {
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nested_vmx_cr_fixed1_bits_update(vcpu);
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nested_vmx_entry_exit_ctls_update(vcpu);
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}
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}
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static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
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@ -12049,8 +12055,13 @@ static void prepare_vmcs02_full(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
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set_cr4_guest_host_mask(vmx);
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if (vmx_mpx_supported())
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vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
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if (kvm_mpx_supported()) {
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if (vmx->nested.nested_run_pending &&
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(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
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vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
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else
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vmcs_write64(GUEST_BNDCFGS, vmx->nested.vmcs01_guest_bndcfgs);
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}
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if (enable_vpid) {
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if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02)
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@ -12595,15 +12606,21 @@ static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, u32 *exit_qual)
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struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
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bool from_vmentry = !!exit_qual;
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u32 dummy_exit_qual;
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u32 vmcs01_cpu_exec_ctrl;
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bool evaluate_pending_interrupts;
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int r = 0;
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vmcs01_cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
|
||||
evaluate_pending_interrupts = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
|
||||
(CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING);
|
||||
if (likely(!evaluate_pending_interrupts) && kvm_vcpu_apicv_active(vcpu))
|
||||
evaluate_pending_interrupts |= vmx_has_apicv_interrupt(vcpu);
|
||||
|
||||
enter_guest_mode(vcpu);
|
||||
|
||||
if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
|
||||
vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
|
||||
if (kvm_mpx_supported() &&
|
||||
!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
|
||||
vmx->nested.vmcs01_guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
|
||||
|
||||
vmx_switch_vmcs(vcpu, &vmx->nested.vmcs02);
|
||||
vmx_segment_cache_clear(vmx);
|
||||
|
|
@ -12643,16 +12660,14 @@ static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, u32 *exit_qual)
|
|||
* to L1 or delivered directly to L2 (e.g. In case L1 don't
|
||||
* intercept EXTERNAL_INTERRUPT).
|
||||
*
|
||||
* Usually this would be handled by L0 requesting a
|
||||
* IRQ/NMI window by setting VMCS accordingly. However,
|
||||
* this setting was done on VMCS01 and now VMCS02 is active
|
||||
* instead. Thus, we force L0 to perform pending event
|
||||
* evaluation by requesting a KVM_REQ_EVENT.
|
||||
* Usually this would be handled by the processor noticing an
|
||||
* IRQ/NMI window request, or checking RVI during evaluation of
|
||||
* pending virtual interrupts. However, this setting was done
|
||||
* on VMCS01 and now VMCS02 is active instead. Thus, we force L0
|
||||
* to perform pending event evaluation by requesting a KVM_REQ_EVENT.
|
||||
*/
|
||||
if (vmcs01_cpu_exec_ctrl &
|
||||
(CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_VIRTUAL_NMI_PENDING)) {
|
||||
if (unlikely(evaluate_pending_interrupts))
|
||||
kvm_make_request(KVM_REQ_EVENT, vcpu);
|
||||
}
|
||||
|
||||
/*
|
||||
* Note no nested_vmx_succeed or nested_vmx_fail here. At this point
|
||||
|
|
|
|||
|
|
@ -4698,7 +4698,7 @@ static void kvm_init_msr_list(void)
|
|||
*/
|
||||
switch (msrs_to_save[i]) {
|
||||
case MSR_IA32_BNDCFGS:
|
||||
if (!kvm_x86_ops->mpx_supported())
|
||||
if (!kvm_mpx_supported())
|
||||
continue;
|
||||
break;
|
||||
case MSR_TSC_AUX:
|
||||
|
|
|
|||
|
|
@ -1325,7 +1325,7 @@ class Tui(object):
|
|||
msg = ''
|
||||
while True:
|
||||
self.screen.erase()
|
||||
self.screen.addstr(0, 0, 'Set update interval (defaults to %fs).' %
|
||||
self.screen.addstr(0, 0, 'Set update interval (defaults to %.1fs).' %
|
||||
DELAY_DEFAULT, curses.A_BOLD)
|
||||
self.screen.addstr(4, 0, msg)
|
||||
self.screen.addstr(2, 0, 'Change delay from %.1fs to ' %
|
||||
|
|
|
|||
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