perf vendor events amd: Add recommended events
Add support for events listed in Section 2.1.15.2 "Performance
Measurement" of "PPR for AMD Family 17h Model 31h B0 - 55803
Rev 0.54 - Sep 12, 2019".
perf now supports these new events (-e):
all_dc_accesses
all_tlbs_flushed
l1_dtlb_misses
l2_cache_accesses_from_dc_misses
l2_cache_accesses_from_ic_misses
l2_cache_hits_from_dc_misses
l2_cache_hits_from_ic_misses
l2_cache_misses_from_dc_misses
l2_cache_misses_from_ic_miss
l2_dtlb_misses
l2_itlb_misses
sse_avx_stalls
uops_dispatched
uops_retired
l3_accesses
l3_misses
and these metrics (-M):
branch_misprediction_ratio
all_l2_cache_accesses
all_l2_cache_hits
all_l2_cache_misses
ic_fetch_miss_ratio
l2_cache_accesses_from_l2_hwpf
l2_cache_hits_from_l2_hwpf
l2_cache_misses_from_l2_hwpf
l3_read_miss_latency
l1_itlb_misses
all_remote_links_outbound
nps1_die_to_dram
The nps1_die_to_dram event may need perf stat's --metric-no-group
switch if the number of available data fabric counters is less
than the number it uses (8).
Committer testing:
On a AMD Ryzen 3900x system:
Before:
# perf list all_dc_accesses all_tlbs_flushed l1_dtlb_misses l2_cache_accesses_from_dc_misses l2_cache_accesses_from_ic_misses l2_cache_hits_from_dc_misses l2_cache_hits_from_ic_misses l2_cache_misses_from_dc_misses l2_cache_misses_from_ic_miss l2_dtlb_misses l2_itlb_misses sse_avx_stalls uops_dispatched uops_retired l3_accesses l3_misses | grep -v "^Metric Groups:$" | grep -v "^$"
#
After:
# perf list all_dc_accesses all_tlbs_flushed l1_dtlb_misses l2_cache_accesses_from_dc_misses l2_cache_accesses_from_ic_misses l2_cache_hits_from_dc_misses l2_cache_hits_from_ic_misses l2_cache_misses_from_dc_misses l2_cache_misses_from_ic_miss l2_dtlb_misses l2_itlb_misses sse_avx_stalls uops_dispatched uops_retired l3_accesses l3_misses | grep -v "^Metric Groups:$" | grep -v "^$" | grep -v "^recommended:$"
all_dc_accesses
[All L1 Data Cache Accesses]
all_tlbs_flushed
[All TLBs Flushed]
l1_dtlb_misses
[L1 DTLB Misses]
l2_cache_accesses_from_dc_misses
[L2 Cache Accesses from L1 Data Cache Misses (including prefetch)]
l2_cache_accesses_from_ic_misses
[L2 Cache Accesses from L1 Instruction Cache Misses (including
prefetch)]
l2_cache_hits_from_dc_misses
[L2 Cache Hits from L1 Data Cache Misses]
l2_cache_hits_from_ic_misses
[L2 Cache Hits from L1 Instruction Cache Misses]
l2_cache_misses_from_dc_misses
[L2 Cache Misses from L1 Data Cache Misses]
l2_cache_misses_from_ic_miss
[L2 Cache Misses from L1 Instruction Cache Misses]
l2_dtlb_misses
[L2 DTLB Misses & Data page walks]
l2_itlb_misses
[L2 ITLB Misses & Instruction page walks]
sse_avx_stalls
[Mixed SSE/AVX Stalls]
uops_dispatched
[Micro-ops Dispatched]
uops_retired
[Micro-ops Retired]
l3_accesses
[L3 Accesses. Unit: amd_l3]
l3_misses
[L3 Misses (includes Chg2X). Unit: amd_l3]
#
# perf stat -a -e all_dc_accesses,all_tlbs_flushed,l1_dtlb_misses,l2_cache_accesses_from_dc_misses,l2_cache_accesses_from_ic_misses,l2_cache_hits_from_dc_misses,l2_cache_hits_from_ic_misses,l2_cache_misses_from_dc_misses,l2_cache_misses_from_ic_miss,l2_dtlb_misses,l2_itlb_misses,sse_avx_stalls,uops_dispatched,uops_retired,l3_accesses,l3_misses sleep 2
Performance counter stats for 'system wide':
433,439,949 all_dc_accesses (35.66%)
443 all_tlbs_flushed (35.66%)
2,985,885 l1_dtlb_misses (35.66%)
18,318,019 l2_cache_accesses_from_dc_misses (35.68%)
50,114,810 l2_cache_accesses_from_ic_misses (35.72%)
12,423,978 l2_cache_hits_from_dc_misses (35.74%)
40,703,103 l2_cache_hits_from_ic_misses (35.74%)
6,698,673 l2_cache_misses_from_dc_misses (35.74%)
12,090,892 l2_cache_misses_from_ic_miss (35.74%)
614,267 l2_dtlb_misses (35.74%)
216,036 l2_itlb_misses (35.74%)
11,977 sse_avx_stalls (35.74%)
999,276,223 uops_dispatched (35.73%)
1,075,311,620 uops_retired (35.69%)
1,420,763 l3_accesses
540,164 l3_misses
2.002344121 seconds time elapsed
# perf stat -a -e all_dc_accesses,all_tlbs_flushed,l1_dtlb_misses,l2_cache_accesses_from_dc_misses,l2_cache_accesses_from_ic_misses sleep 2
Performance counter stats for 'system wide':
175,943,104 all_dc_accesses
310 all_tlbs_flushed
2,280,359 l1_dtlb_misses
11,700,151 l2_cache_accesses_from_dc_misses
25,414,963 l2_cache_accesses_from_ic_misses
2.001957818 seconds time elapsed
#
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Jin Yao <yao.jin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Jon Grimm <jon.grimm@amd.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Martin Jambor <mjambor@suse.cz>
Cc: Martin Liška <mliska@suse.cz>
Cc: Michael Petlan <mpetlan@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Vijay Thakkar <vijaythakkar@me.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: Yunfeng Ye <yeyunfeng@huawei.com>
Link: http://lore.kernel.org/lkml/20200901220944.277505-3-kim.phillips@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Kim Phillips
Arnaldo Carvalho de Melo
Родитель
ab22eea35f
Коммит
08ed77e414
|
|
@ -117,6 +117,11 @@
|
|||
"BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.all_no_prefetch",
|
||||
"EventCode": "0x60",
|
||||
"UMask": "0xf9"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g2.group1",
|
||||
"EventCode": "0x61",
|
||||
|
|
@ -243,6 +248,24 @@
|
|||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_access_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.",
|
||||
"UMask": "0x7"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
|
||||
"UMask": "0x9"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
|
||||
"UMask": "0xf6"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_pending.l2_fill_busy",
|
||||
"EventCode": "0x6d",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
[
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_0",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0",
|
||||
"EventCode": "0x7c7",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_1",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1",
|
||||
"EventCode": "0x807",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_2",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2",
|
||||
"EventCode": "0x847",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_3",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3",
|
||||
"EventCode": "0x887",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_0",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x07",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_1",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x47",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_2",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x87",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_3",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0xc7",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_4",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x107",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_5",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x147",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_6",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x187",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_7",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x1c7",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
[
|
||||
{
|
||||
"MetricName": "branch_misprediction_ratio",
|
||||
"BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
|
||||
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
|
||||
"MetricGroup": "branch_prediction",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"EventName": "all_dc_accesses",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "All L1 Data Cache Accesses",
|
||||
"UMask": "0x7"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_accesses",
|
||||
"BriefDescription": "All L2 Cache Accesses",
|
||||
"MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_accesses_from_ic_misses",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_accesses_from_dc_misses",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
|
||||
"UMask": "0xc8"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_accesses_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Accesses from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_misses",
|
||||
"BriefDescription": "All L2 Cache Misses",
|
||||
"MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_misses_from_ic_miss",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_misses_from_dc_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_misses_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Misses from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_hits",
|
||||
"BriefDescription": "All L2 Cache Hits",
|
||||
"MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_hits_from_ic_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
|
||||
"UMask": "0x06"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_hits_from_dc_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
|
||||
"UMask": "0x70"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_hits_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Hits from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l3_accesses",
|
||||
"EventCode": "0x04",
|
||||
"BriefDescription": "L3 Accesses",
|
||||
"UMask": "0xff",
|
||||
"Unit": "L3PMC"
|
||||
},
|
||||
{
|
||||
"EventName": "l3_misses",
|
||||
"EventCode": "0x04",
|
||||
"BriefDescription": "L3 Misses (includes Chg2X)",
|
||||
"UMask": "0x01",
|
||||
"Unit": "L3PMC"
|
||||
},
|
||||
{
|
||||
"MetricName": "l3_read_miss_latency",
|
||||
"BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
|
||||
"MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs",
|
||||
"MetricGroup": "l3_cache",
|
||||
"ScaleUnit": "1core clocks"
|
||||
},
|
||||
{
|
||||
"MetricName": "ic_fetch_miss_ratio",
|
||||
"BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
|
||||
"MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)",
|
||||
"MetricGroup": "l2_cache",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1_itlb_misses",
|
||||
"BriefDescription": "L1 ITLB Misses",
|
||||
"MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss",
|
||||
"MetricGroup": "tlb"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_itlb_misses",
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "L2 ITLB Misses & Instruction page walks",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "l1_dtlb_misses",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB Misses",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_dtlb_misses",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L2 DTLB Misses & Data page walks",
|
||||
"UMask": "0xf0"
|
||||
},
|
||||
{
|
||||
"EventName": "all_tlbs_flushed",
|
||||
"EventCode": "0x78",
|
||||
"BriefDescription": "All TLBs Flushed",
|
||||
"UMask": "0xdf"
|
||||
},
|
||||
{
|
||||
"EventName": "uops_dispatched",
|
||||
"EventCode": "0xaa",
|
||||
"BriefDescription": "Micro-ops Dispatched",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "sse_avx_stalls",
|
||||
"EventCode": "0x0e",
|
||||
"BriefDescription": "Mixed SSE/AVX Stalls",
|
||||
"UMask": "0x0e"
|
||||
},
|
||||
{
|
||||
"EventName": "uops_retired",
|
||||
"EventCode": "0xc1",
|
||||
"BriefDescription": "Micro-ops Retired"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_remote_links_outbound",
|
||||
"BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
|
||||
"MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
|
||||
"MetricGroup": "data_fabric",
|
||||
"PerPkg": "1",
|
||||
"ScaleUnit": "3e-5MiB"
|
||||
},
|
||||
{
|
||||
"MetricName": "nps1_die_to_dram",
|
||||
"BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
|
||||
"MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
|
||||
"MetricGroup": "data_fabric",
|
||||
"PerPkg": "1",
|
||||
"ScaleUnit": "6.1e-5MiB"
|
||||
}
|
||||
]
|
||||
|
|
@ -47,6 +47,11 @@
|
|||
"BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g1.all_no_prefetch",
|
||||
"EventCode": "0x60",
|
||||
"UMask": "0xf9"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_request_g2.group1",
|
||||
"EventCode": "0x61",
|
||||
|
|
@ -173,6 +178,24 @@
|
|||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.",
|
||||
"UMask": "0x1"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_access_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.",
|
||||
"UMask": "0x7"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
|
||||
"UMask": "0x9"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
|
||||
"UMask": "0xf6"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_fill_pending.l2_fill_busy",
|
||||
"EventCode": "0x6d",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,98 @@
|
|||
[
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_0",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0",
|
||||
"EventCode": "0x7c7",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_1",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1",
|
||||
"EventCode": "0x807",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_2",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2",
|
||||
"EventCode": "0x847",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "remote_outbound_data_controller_3",
|
||||
"PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3",
|
||||
"EventCode": "0x887",
|
||||
"UMask": "0x02",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_0",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x07",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_1",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x47",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_2",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x87",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_3",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0xc7",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_4",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x107",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_5",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x147",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_6",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x187",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
},
|
||||
{
|
||||
"EventName": "dram_channel_data_controller_7",
|
||||
"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
|
||||
"EventCode": "0x1c7",
|
||||
"UMask": "0x38",
|
||||
"PerPkg": "1",
|
||||
"Unit": "DFPMC"
|
||||
}
|
||||
]
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
[
|
||||
{
|
||||
"MetricName": "branch_misprediction_ratio",
|
||||
"BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
|
||||
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
|
||||
"MetricGroup": "branch_prediction",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"EventName": "all_dc_accesses",
|
||||
"EventCode": "0x29",
|
||||
"BriefDescription": "All L1 Data Cache Accesses",
|
||||
"UMask": "0x7"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_accesses",
|
||||
"BriefDescription": "All L2 Cache Accesses",
|
||||
"MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_accesses_from_ic_misses",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
|
||||
"UMask": "0x10"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_accesses_from_dc_misses",
|
||||
"EventCode": "0x60",
|
||||
"BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
|
||||
"UMask": "0xc8"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_accesses_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Accesses from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_misses",
|
||||
"BriefDescription": "All L2 Cache Misses",
|
||||
"MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_misses_from_ic_miss",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
|
||||
"UMask": "0x01"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_misses_from_dc_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
|
||||
"UMask": "0x08"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_misses_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Misses from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_l2_cache_hits",
|
||||
"BriefDescription": "All L2 Cache Hits",
|
||||
"MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_hits_from_ic_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
|
||||
"UMask": "0x06"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_cache_hits_from_dc_misses",
|
||||
"EventCode": "0x64",
|
||||
"BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
|
||||
"UMask": "0x70"
|
||||
},
|
||||
{
|
||||
"MetricName": "l2_cache_hits_from_l2_hwpf",
|
||||
"BriefDescription": "L2 Cache Hits from L2 HWPF",
|
||||
"MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
|
||||
"MetricGroup": "l2_cache"
|
||||
},
|
||||
{
|
||||
"EventName": "l3_accesses",
|
||||
"EventCode": "0x04",
|
||||
"BriefDescription": "L3 Accesses",
|
||||
"UMask": "0xff",
|
||||
"Unit": "L3PMC"
|
||||
},
|
||||
{
|
||||
"EventName": "l3_misses",
|
||||
"EventCode": "0x04",
|
||||
"BriefDescription": "L3 Misses (includes Chg2X)",
|
||||
"UMask": "0x01",
|
||||
"Unit": "L3PMC"
|
||||
},
|
||||
{
|
||||
"MetricName": "l3_read_miss_latency",
|
||||
"BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
|
||||
"MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs",
|
||||
"MetricGroup": "l3_cache",
|
||||
"ScaleUnit": "1core clocks"
|
||||
},
|
||||
{
|
||||
"MetricName": "ic_fetch_miss_ratio",
|
||||
"BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
|
||||
"MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)",
|
||||
"MetricGroup": "l2_cache",
|
||||
"ScaleUnit": "100%"
|
||||
},
|
||||
{
|
||||
"MetricName": "l1_itlb_misses",
|
||||
"BriefDescription": "L1 ITLB Misses",
|
||||
"MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss",
|
||||
"MetricGroup": "tlb"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_itlb_misses",
|
||||
"EventCode": "0x85",
|
||||
"BriefDescription": "L2 ITLB Misses & Instruction page walks",
|
||||
"UMask": "0x07"
|
||||
},
|
||||
{
|
||||
"EventName": "l1_dtlb_misses",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L1 DTLB Misses",
|
||||
"UMask": "0xff"
|
||||
},
|
||||
{
|
||||
"EventName": "l2_dtlb_misses",
|
||||
"EventCode": "0x45",
|
||||
"BriefDescription": "L2 DTLB Misses & Data page walks",
|
||||
"UMask": "0xf0"
|
||||
},
|
||||
{
|
||||
"EventName": "all_tlbs_flushed",
|
||||
"EventCode": "0x78",
|
||||
"BriefDescription": "All TLBs Flushed",
|
||||
"UMask": "0xdf"
|
||||
},
|
||||
{
|
||||
"EventName": "uops_dispatched",
|
||||
"EventCode": "0xaa",
|
||||
"BriefDescription": "Micro-ops Dispatched",
|
||||
"UMask": "0x03"
|
||||
},
|
||||
{
|
||||
"EventName": "sse_avx_stalls",
|
||||
"EventCode": "0x0e",
|
||||
"BriefDescription": "Mixed SSE/AVX Stalls",
|
||||
"UMask": "0x0e"
|
||||
},
|
||||
{
|
||||
"EventName": "uops_retired",
|
||||
"EventCode": "0xc1",
|
||||
"BriefDescription": "Micro-ops Retired"
|
||||
},
|
||||
{
|
||||
"MetricName": "all_remote_links_outbound",
|
||||
"BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
|
||||
"MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
|
||||
"MetricGroup": "data_fabric",
|
||||
"PerPkg": "1",
|
||||
"ScaleUnit": "3e-5MiB"
|
||||
},
|
||||
{
|
||||
"MetricName": "nps1_die_to_dram",
|
||||
"BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
|
||||
"MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
|
||||
"MetricGroup": "data_fabric",
|
||||
"PerPkg": "1",
|
||||
"ScaleUnit": "6.1e-5MiB"
|
||||
}
|
||||
]
|
||||
|
|
@ -240,6 +240,7 @@ static struct map {
|
|||
{ "hisi_sccl,hha", "hisi_sccl,hha" },
|
||||
{ "hisi_sccl,l3c", "hisi_sccl,l3c" },
|
||||
{ "L3PMC", "amd_l3" },
|
||||
{ "DFPMC", "amd_df" },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче