EDAC, altera: Merge Stratix10 into the Arria10 SDRAM probe routine
Change Stratix10 regmap to use offsets from a base to match the Arria10 regmap and allow re-use of the Arria10 functions. Only the regmap initialization differs (Arria10 mmio_regmap vs Stratix10 custom regmap). Modify the SDRAM probe function to handle Stratix10. Remove the Stratix10 offset defines if Arria10 can be used. Remove the unused Stratix10 probe function. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: dinguyen@kernel.org Cc: robh+dt@kernel.org Cc: mark.rutland@arm.com Cc: mchehab@kernel.org Cc: devicetree@vger.kernel.org Cc: linux-edac@vger.kernel.org Link: https://lkml.kernel.org/r/1537883342-30180-5-git-send-email-thor.thayer@linux.intel.com
This commit is contained in:
Родитель
446fd7afdc
Коммит
08f08bfb7b
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@ -69,25 +69,6 @@ static const struct altr_sdram_prv_data a10_data = {
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.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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};
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static const struct altr_sdram_prv_data s10_data = {
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.ecc_ctrl_offset = S10_ECCCTRL1_OFST,
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.ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
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.ecc_stat_offset = S10_INTSTAT_OFST,
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.ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
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.ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
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.ecc_saddr_offset = S10_SERRADDR_OFST,
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.ecc_daddr_offset = S10_DERRADDR_OFST,
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.ecc_irq_en_offset = S10_ERRINTEN_OFST,
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.ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
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.ecc_irq_clr_offset = S10_INTSTAT_OFST,
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.ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
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.ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
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.ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
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.ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
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.ce_set_mask = A10_DIAGINT_TSERRA_MASK,
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.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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};
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/*********************** EDAC Memory Controller Functions ****************/
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/* The SDRAM controller uses the EDAC Memory Controller framework. */
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@ -239,7 +220,7 @@ static unsigned long get_total_mem(void)
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", .data = &c5_data},
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{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
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{ .compatible = "altr,sdram-edac-s10", .data = &s10_data},
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{ .compatible = "altr,sdram-edac-s10", .data = &a10_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
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@ -293,6 +274,7 @@ release:
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return ret;
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}
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static int socfpga_is_a10(void);
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static int altr_sdram_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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@ -416,7 +398,7 @@ static int altr_sdram_probe(struct platform_device *pdev)
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goto err;
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/* Only the Arria10 has separate IRQs */
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if (irq2 > 0) {
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if (socfpga_is_a10()) {
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/* Arria10 specific initialization */
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res = a10_init(mc_vbase);
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if (res < 0)
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@ -502,8 +484,9 @@ static int s10_protected_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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struct arm_smccc_res result;
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unsigned long offset = (unsigned long)context;
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arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
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arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0,
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0, 0, 0, &result);
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return (int)result.a0;
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@ -523,8 +506,9 @@ static int s10_protected_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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struct arm_smccc_res result;
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unsigned long offset = (unsigned long)context;
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arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
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arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0,
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0, 0, 0, &result);
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*val = (unsigned int)result.a1;
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@ -532,245 +516,17 @@ static int s10_protected_reg_read(void *context, unsigned int reg,
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return (int)result.a0;
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}
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static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case S10_ECCCTRL1_OFST:
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case S10_ERRINTEN_OFST:
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case S10_INTMODE_OFST:
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case S10_INTSTAT_OFST:
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case S10_DIAGINTTEST_OFST:
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case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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return true;
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}
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return false;
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}
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static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case S10_ECCCTRL1_OFST:
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case S10_ERRINTEN_OFST:
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case S10_INTMODE_OFST:
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case S10_INTSTAT_OFST:
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case S10_DERRADDR_OFST:
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case S10_SERRADDR_OFST:
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case S10_DIAGINTTEST_OFST:
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case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
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case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
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return true;
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}
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return false;
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}
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static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case S10_ECCCTRL1_OFST:
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case S10_ERRINTEN_OFST:
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case S10_INTMODE_OFST:
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case S10_INTSTAT_OFST:
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case S10_DERRADDR_OFST:
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case S10_SERRADDR_OFST:
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case S10_DIAGINTTEST_OFST:
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case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
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case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
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return true;
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}
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return false;
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}
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static const struct regmap_config s10_sdram_regmap_cfg = {
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.name = "s10_ddr",
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xffffffff,
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.writeable_reg = s10_sdram_writeable_reg,
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.readable_reg = s10_sdram_readable_reg,
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.volatile_reg = s10_sdram_volatile_reg,
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.max_register = 0xffd12228,
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.reg_read = s10_protected_reg_read,
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.reg_write = s10_protected_reg_write,
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.use_single_rw = true,
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};
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static int altr_s10_sdram_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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struct altr_sdram_mc_data *drvdata;
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const struct altr_sdram_prv_data *priv;
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struct regmap *regmap;
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struct dimm_info *dimm;
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u32 read_reg;
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int irq, ret = 0;
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unsigned long mem_size;
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id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
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if (!id)
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return -ENODEV;
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/* Grab specific offsets and masks for Stratix10 */
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priv = of_match_node(altr_sdram_ctrl_of_match,
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pdev->dev.of_node)->data;
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regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
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&s10_sdram_regmap_cfg);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Validate the SDRAM controller has ECC enabled */
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if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) ||
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((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No ECC/ECC disabled [0x%08X]\n", read_reg);
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return -ENODEV;
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}
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/* Grab memory size from device tree. */
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mem_size = get_total_mem();
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if (!mem_size) {
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edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
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return -ENODEV;
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}
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/* Ensure the SDRAM Interrupt is disabled */
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if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
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priv->ecc_irq_en_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error disabling SDRAM ECC IRQ\n");
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return -ENODEV;
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}
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/* Toggle to clear the SDRAM Error count */
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if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask,
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priv->ecc_cnt_rst_mask)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
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priv->ecc_cnt_rst_mask, 0)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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return -ENODEV;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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edac_printk(KERN_ERR, EDAC_MC,
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"No irq %d in DT\n", irq);
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return -ENODEV;
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}
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = 1;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = 1;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct altr_sdram_mc_data));
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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drvdata = mci->pvt_info;
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drvdata->mc_vbase = regmap;
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drvdata->data = priv;
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platform_set_drvdata(pdev, mci);
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if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Unable to get managed device resource\n");
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ret = -ENOMEM;
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goto free;
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}
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mci->mtype_cap = MEM_FLAG_DDR3;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->mod_name = EDAC_MOD_STR;
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mci->ctl_name = dev_name(&pdev->dev);
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mci->scrub_mode = SCRUB_SW_SRC;
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mci->dev_name = dev_name(&pdev->dev);
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dimm = *mci->dimms;
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dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
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dimm->grain = 8;
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dimm->dtype = DEV_X8;
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dimm->mtype = MEM_DDR3;
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dimm->edac_mode = EDAC_SECDED;
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ret = edac_mc_add_mc(mci);
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if (ret < 0)
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goto err;
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ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
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IRQF_SHARED, dev_name(&pdev->dev), mci);
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if (ret < 0) {
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edac_mc_printk(mci, KERN_ERR,
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"Unable to request irq %d\n", irq);
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ret = -ENODEV;
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goto err2;
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}
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if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
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S10_DDR0_IRQ_MASK)) {
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edac_printk(KERN_ERR, EDAC_MC,
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"Error clearing SDRAM ECC count\n");
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ret = -ENODEV;
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goto err2;
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}
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if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
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priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
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edac_mc_printk(mci, KERN_ERR,
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"Error enabling SDRAM ECC IRQ\n");
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ret = -ENODEV;
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goto err2;
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}
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altr_sdr_mc_create_debugfs_nodes(mci);
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devres_close_group(&pdev->dev, NULL);
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return 0;
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err2:
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edac_mc_del_mc(&pdev->dev);
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err:
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devres_release_group(&pdev->dev, NULL);
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free:
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edac_mc_free(mci);
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edac_printk(KERN_ERR, EDAC_MC,
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"EDAC Probe Failed; Error %d\n", ret);
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return ret;
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}
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static int altr_s10_sdram_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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/************** </Stratix10 EDAC Memory Controller Functions> ***********/
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/*
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@ -804,20 +560,6 @@ static struct platform_driver altr_sdram_edac_driver = {
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module_platform_driver(altr_sdram_edac_driver);
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static struct platform_driver altr_s10_sdram_edac_driver = {
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.probe = altr_s10_sdram_probe,
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.remove = altr_s10_sdram_remove,
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.driver = {
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.name = "altr_s10_sdram_edac",
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#ifdef CONFIG_PM
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.pm = &altr_sdram_pm_ops,
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#endif
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.of_match_table = altr_sdram_ctrl_of_match,
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},
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};
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module_platform_driver(altr_s10_sdram_edac_driver);
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/************************* EDAC Parent Probe *************************/
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static const struct of_device_id altr_edac_device_of_match[];
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@ -2163,7 +1905,7 @@ static int s10_edac_dberr_handler(struct notifier_block *this,
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&dberror);
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regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
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if (dberror & S10_DDR0_IRQ_MASK) {
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regmap_read(edac->ecc_mgr_map, S10_DERRADDR_OFST, &err_addr);
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regmap_read(edac->ecc_mgr_map, A10_DERRADDR_OFST, &err_addr);
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regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
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err_addr);
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edac_printk(KERN_ERR, EDAC_MC,
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|
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@ -156,34 +156,6 @@
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#define A10_INTMASK_CLR_OFST 0x10
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#define A10_DDR0_IRQ_MASK BIT(17)
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/************* Stratix10 Defines **************/
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/* SDRAM Controller EccCtrl Register */
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#define S10_ECCCTRL1_OFST 0xF8011100
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/* SDRAM Controller DRAM IRQ Register */
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#define S10_ERRINTEN_OFST 0xF8011110
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/* SDRAM Interrupt Mode Register */
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#define S10_INTMODE_OFST 0xF801111C
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/* SDRAM Controller Error Status Register */
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#define S10_INTSTAT_OFST 0xF8011120
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/* SDRAM Controller ECC Error Address Register */
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#define S10_DERRADDR_OFST 0xF801112C
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#define S10_SERRADDR_OFST 0xF8011130
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/* SDRAM Controller ECC Diagnostic Register */
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#define S10_DIAGINTTEST_OFST 0xF8011124
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/* SDRAM Single Bit Error Count Compare Set Register */
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#define S10_SERRCNTREG_OFST 0xF801113C
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/* Sticky registers for Uncorrected Errors */
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#define S10_SYSMGR_UE_VAL_OFST 0xFFD12220
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#define S10_SYSMGR_UE_ADDR_OFST 0xFFD12224
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struct altr_sdram_prv_data {
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int ecc_ctrl_offset;
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int ecc_ctl_en_mask;
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|
@ -319,12 +291,12 @@ struct altr_sdram_mc_data {
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/************* Stratix10 Defines **************/
|
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/* Stratix10 ECC Manager Defines */
|
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#define S10_SYSMGR_ECC_INTMASK_VAL_OFST 0xFFD12090
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#define S10_SYSMGR_ECC_INTMASK_SET_OFST 0xFFD12094
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#define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0xFFD12098
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#define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
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#define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
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#define S10_SYSMGR_ECC_INTSTAT_SERR_OFST 0xFFD1209C
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#define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xFFD120A0
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/* Sticky registers for Uncorrected Errors */
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#define S10_SYSMGR_UE_VAL_OFST 0x120
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#define S10_SYSMGR_UE_ADDR_OFST 0x124
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#define S10_DDR0_IRQ_MASK BIT(16)
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