mmc: sdhci-of-dwcmshc: add rockchip platform support
sdhci based synopsys MMC IP is also used on some rockchip platforms, so add a basic support here. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/1615879102-45919-3-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Shawn Lin
Ulf Hansson
Родитель
dd12261e7f
Коммит
08f3dff799
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@ -9,9 +9,11 @@
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/sizes.h>
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#include "sdhci-pltfm.h"
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@ -21,11 +23,52 @@
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/* DWCMSHC specific Mode Select value */
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#define DWCMSHC_CTRL_HS400 0x7
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/* DWC IP vendor area 1 pointer */
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#define DWCMSHC_P_VENDOR_AREA1 0xe8
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#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
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/* Offset inside the vendor area 1 */
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#define DWCMSHC_HOST_CTRL3 0x8
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#define DWCMSHC_EMMC_CONTROL 0x2c
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#define DWCMSHC_ENHANCED_STROBE BIT(8)
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#define DWCMSHC_EMMC_ATCTRL 0x40
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/* Rockchip specific Registers */
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
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#define DWCMSHC_EMMC_DLL_TXCLK 0x808
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#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
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#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
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#define DWCMSHC_EMMC_DLL_STATUS0 0x840
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#define DWCMSHC_EMMC_DLL_START BIT(0)
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#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
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#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
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#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
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#define DWCMSHC_EMMC_DLL_START_POINT 16
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#define DWCMSHC_EMMC_DLL_INC 8
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#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x8
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#define DLL_STRBIN_TAPNUM_DEFAULT 0x8
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#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
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#define DLL_RXCLK_NO_INVERTER 1
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#define DLL_RXCLK_INVERTER 0
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#define DLL_LOCK_WO_TMOUT(x) \
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((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
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(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
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#define RK3568_MAX_CLKS 3
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#define BOUNDARY_OK(addr, len) \
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((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
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struct rk3568_priv {
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/* Rockchip specified optional clocks */
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struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS];
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u8 txclk_tapnum;
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};
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struct dwcmshc_priv {
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struct clk *bus_clk;
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int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
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void *priv; /* pointer to SoC private stuff */
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};
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/*
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@ -100,6 +143,107 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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u32 vendor;
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
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vendor = sdhci_readl(host, reg);
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if (ios->enhanced_strobe)
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vendor |= DWCMSHC_ENHANCED_STROBE;
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else
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vendor &= ~DWCMSHC_ENHANCED_STROBE;
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sdhci_writel(host, vendor, reg);
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}
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static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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struct rk3568_priv *priv = dwc_priv->priv;
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u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
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u32 extra, reg;
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int err;
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host->mmc->actual_clock = 0;
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/*
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* DO NOT TOUCH THIS SETTING. RX clk inverter unit is enabled
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* by default, but it shouldn't be enabled. We should anyway
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* disable it before issuing any cmds.
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*/
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
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if (clock == 0)
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return;
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/* Rockchip platform only support 375KHz for identify mode */
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if (clock <= 400000)
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clock = 375000;
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err = clk_set_rate(pltfm_host->clk, clock);
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if (err)
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dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
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sdhci_set_clock(host, clock);
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/* Disable cmd conflict check */
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reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
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extra = sdhci_readl(host, reg);
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extra &= ~BIT(0);
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sdhci_writel(host, extra, reg);
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if (clock <= 400000) {
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/* Disable DLL to reset sample clock */
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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return;
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}
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/* Reset DLL */
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sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
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udelay(1);
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sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
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/* Init DLL settings */
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extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
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0x2 << DWCMSHC_EMMC_DLL_INC |
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DWCMSHC_EMMC_DLL_START;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
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err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
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extra, DLL_LOCK_WO_TMOUT(extra), 1,
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500 * USEC_PER_MSEC);
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if (err) {
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dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
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return;
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}
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extra = 0x1 << 16 | /* tune clock stop en */
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0x2 << 17 | /* pre-change delay */
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0x3 << 19; /* post-change delay */
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sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
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host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
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txclk_tapnum = priv->txclk_tapnum;
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_TXCLK_TAPNUM_FROM_SW |
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txclk_tapnum;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
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extra = DWCMSHC_EMMC_DLL_DLYENA |
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DLL_STRBIN_TAPNUM_DEFAULT |
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DLL_STRBIN_TAPNUM_FROM_SW;
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sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
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}
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static const struct sdhci_ops sdhci_dwcmshc_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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@ -109,21 +253,93 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = {
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = {
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.set_clock = dwcmshc_rk3568_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.reset = sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
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.ops = &sdhci_dwcmshc_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3568_pdata = {
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.ops = &sdhci_dwcmshc_rk3568_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
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SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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};
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static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
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{
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int err;
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struct rk3568_priv *priv = dwc_priv->priv;
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priv->rockchip_clks[0].id = "axi";
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priv->rockchip_clks[1].id = "block";
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priv->rockchip_clks[2].id = "timer";
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err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK3568_MAX_CLKS,
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priv->rockchip_clks);
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if (err) {
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dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
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return err;
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}
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err = clk_bulk_prepare_enable(RK3568_MAX_CLKS, priv->rockchip_clks);
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if (err) {
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dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
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return err;
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}
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if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
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&priv->txclk_tapnum))
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priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
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/* Disable cmd conflict check */
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sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
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/* Reset previous settings */
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
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return 0;
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}
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static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
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{
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.compatible = "rockchip,rk3568-dwcmshc",
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.data = &sdhci_dwcmshc_rk3568_pdata,
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},
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{
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.compatible = "snps,dwcmshc-sdhci",
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.data = &sdhci_dwcmshc_pdata,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
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static int dwcmshc_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_host *host;
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struct dwcmshc_priv *priv;
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struct rk3568_priv *rk_priv = NULL;
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const struct sdhci_pltfm_data *pltfm_data;
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int err;
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u32 extra;
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host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
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pltfm_data = of_device_get_match_data(&pdev->dev);
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if (!pltfm_data) {
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dev_err(&pdev->dev, "Error: No device match data found\n");
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return -ENODEV;
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}
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host = sdhci_pltfm_init(pdev, pltfm_data,
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sizeof(struct dwcmshc_priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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@ -159,7 +375,23 @@ static int dwcmshc_probe(struct platform_device *pdev)
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sdhci_get_of_property(pdev);
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priv->vendor_specific_area1 =
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sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
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host->mmc_host_ops.request = dwcmshc_request;
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host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
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if (pltfm_data == &sdhci_dwcmshc_rk3568_pdata) {
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rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk3568_priv), GFP_KERNEL);
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if (!rk_priv)
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goto err_clk;
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priv->priv = rk_priv;
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err = dwcmshc_rk3568_init(host, priv);
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if (err)
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goto err_clk;
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}
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err = sdhci_add_host(host);
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if (err)
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@ -170,6 +402,9 @@ static int dwcmshc_probe(struct platform_device *pdev)
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err_clk:
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clk_disable_unprepare(pltfm_host->clk);
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clk_disable_unprepare(priv->bus_clk);
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if (rk_priv)
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clk_bulk_disable_unprepare(RK3568_MAX_CLKS,
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rk_priv->rockchip_clks);
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free_pltfm:
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sdhci_pltfm_free(pdev);
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return err;
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@ -180,12 +415,15 @@ static int dwcmshc_remove(struct platform_device *pdev)
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct rk3568_priv *rk_priv = priv->priv;
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sdhci_remove_host(host, 0);
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clk_disable_unprepare(pltfm_host->clk);
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clk_disable_unprepare(priv->bus_clk);
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if (rk_priv)
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clk_bulk_disable_unprepare(RK3568_MAX_CLKS,
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rk_priv->rockchip_clks);
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sdhci_pltfm_free(pdev);
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return 0;
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@ -197,6 +435,7 @@ static int dwcmshc_suspend(struct device *dev)
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct rk3568_priv *rk_priv = priv->priv;
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int ret;
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ret = sdhci_suspend_host(host);
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@ -207,6 +446,10 @@ static int dwcmshc_suspend(struct device *dev)
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if (!IS_ERR(priv->bus_clk))
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clk_disable_unprepare(priv->bus_clk);
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if (rk_priv)
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clk_bulk_disable_unprepare(RK3568_MAX_CLKS,
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rk_priv->rockchip_clks);
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return ret;
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}
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@ -215,6 +458,7 @@ static int dwcmshc_resume(struct device *dev)
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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struct rk3568_priv *rk_priv = priv->priv;
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int ret;
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ret = clk_prepare_enable(pltfm_host->clk);
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@ -227,18 +471,19 @@ static int dwcmshc_resume(struct device *dev)
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return ret;
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}
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if (rk_priv) {
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ret = clk_bulk_prepare_enable(RK3568_MAX_CLKS,
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rk_priv->rockchip_clks);
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if (ret)
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return ret;
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}
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return sdhci_resume_host(host);
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}
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#endif
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static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
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static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
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{ .compatible = "snps,dwcmshc-sdhci" },
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{}
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};
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MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
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static struct platform_driver sdhci_dwcmshc_driver = {
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.driver = {
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.name = "sdhci-dwcmshc",
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