x86_32: trim memory by updating e820
when MTRRs are not covering the whole e820 table, we need to trim the RAM and need to update e820. reuse some code on 64-bit as well. here need to add early_get_cap and use it in early_cpu_detect, and move mtrr_bp_init early. The code successfully trimmed the memory map on Justin's system: from: [ 0.000000] BIOS-e820: 0000000100000000 - 000000022c000000 (usable) to: [ 0.000000] modified: 0000000100000000 - 0000000228000000 (usable) [ 0.000000] modified: 0000000228000000 - 000000022c000000 (reserved) According to Justin it makes quite a difference: | When I boot the box without any trimming it acts like a 286 or 386, | takes about 10 minutes to boot (using raptor disks). Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Tested-by: Justin Piszcz <jpiszcz@lucidpixels.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -583,7 +583,7 @@ and is between 256 and 4096 characters. It is defined in the file
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See drivers/char/README.epca and
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Documentation/digiepca.txt.
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disable_mtrr_trim [X86-64, Intel only]
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disable_mtrr_trim [X86, Intel and AMD only]
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By default the kernel will trim any uncacheable
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memory out of your available memory pool based on
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MTRR settings. This parameter disables that behavior,
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@ -278,6 +278,33 @@ void __init cpu_detect(struct cpuinfo_x86 *c)
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c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
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}
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}
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static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
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{
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u32 tfms, xlvl;
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int ebx;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (have_cpuid_p()) {
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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}
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}
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}
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/* Do minimum CPU detection early.
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Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
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@ -306,6 +333,8 @@ static void __init early_cpu_detect(void)
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early_init_intel(c);
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break;
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}
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early_get_cap(c);
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}
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static void __cpuinit generic_identify(struct cpuinfo_x86 * c)
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@ -485,7 +514,6 @@ void __init identify_boot_cpu(void)
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identify_cpu(&boot_cpu_data);
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sysenter_setup();
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enable_sep_cpu();
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mtrr_bp_init();
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}
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void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
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@ -624,7 +624,6 @@ static struct sysdev_driver mtrr_sysdev_driver = {
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.resume = mtrr_restore,
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};
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#ifdef CONFIG_X86_64
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static int disable_mtrr_trim;
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static int __init disable_mtrr_trim_setup(char *str)
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@ -643,13 +642,10 @@ early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
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#define Tom2Enabled (1U << 21)
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#define Tom2ForceMemTypeWB (1U << 22)
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static __init int amd_special_default_mtrr(unsigned long end_pfn)
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static __init int amd_special_default_mtrr(void)
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{
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u32 l, h;
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/* Doesn't apply to memory < 4GB */
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if (end_pfn <= (0xffffffff >> PAGE_SHIFT))
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return 0;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return 0;
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if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
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@ -687,9 +683,14 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
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* Make sure we only trim uncachable memory on machines that
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* support the Intel MTRR architecture:
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*/
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if (!is_cpu(INTEL) || disable_mtrr_trim)
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return 0;
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rdmsr(MTRRdefType_MSR, def, dummy);
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def &= 0xff;
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if (!is_cpu(INTEL) || disable_mtrr_trim || def != MTRR_TYPE_UNCACHABLE)
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if (def != MTRR_TYPE_UNCACHABLE)
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return 0;
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if (amd_special_default_mtrr())
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return 0;
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/* Find highest cached pfn */
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@ -703,8 +704,14 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
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highest_addr = base + size;
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}
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if (amd_special_default_mtrr(end_pfn))
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/* kvm/qemu doesn't have mtrr set right, don't trim them all */
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if (!highest_addr) {
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printk(KERN_WARNING "***************\n");
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printk(KERN_WARNING "**** WARNING: likely strange cpu\n");
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printk(KERN_WARNING "**** MTRRs all blank, cpu in qemu?\n");
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printk(KERN_WARNING "***************\n");
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return 0;
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}
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if ((highest_addr >> PAGE_SHIFT) < end_pfn) {
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printk(KERN_WARNING "***************\n");
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@ -726,7 +733,6 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
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return 0;
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}
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#endif
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/**
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* mtrr_bp_init - initialize mtrrs on the boot CPU
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@ -749,3 +749,14 @@ static int __init parse_memmap(char *arg)
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return 0;
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}
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early_param("memmap", parse_memmap);
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void __init update_e820(void)
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{
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u8 nr_map;
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nr_map = e820.nr_map;
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if (sanitize_e820_map(e820.map, &nr_map))
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return;
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e820.nr_map = nr_map;
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printk(KERN_INFO "modified physical RAM map:\n");
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print_memory_map("modified");
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}
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@ -48,6 +48,7 @@
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#include <video/edid.h>
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#include <asm/mtrr.h>
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#include <asm/apic.h>
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#include <asm/e820.h>
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#include <asm/mpspec.h>
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@ -758,6 +759,11 @@ void __init setup_arch(char **cmdline_p)
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max_low_pfn = setup_memory();
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/* update e820 for memory not covered by WB MTRRs */
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mtrr_bp_init();
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if (mtrr_trim_uncached_memory(max_pfn))
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max_low_pfn = setup_memory();
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#ifdef CONFIG_VMI
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/*
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* Must be after max_low_pfn is determined, and before kernel
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@ -19,12 +19,15 @@
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#ifndef __ASSEMBLY__
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extern struct e820map e820;
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extern void update_e820(void);
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extern int e820_all_mapped(unsigned long start, unsigned long end,
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unsigned type);
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extern int e820_any_mapped(u64 start, u64 end, unsigned type);
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extern void find_max_pfn(void);
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extern void register_bootmem_low_pages(unsigned long max_low_pfn);
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extern void add_memory_region(unsigned long long start,
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unsigned long long size, int type);
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extern void e820_register_memory(void);
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extern void limit_regions(unsigned long long size);
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extern void print_memory_map(char *who);
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