irqchip/gic-v3-its: Specialise readq and writeq accesses
readq and writeq type of assessors are not supported in AArch32, so we need to specialise them and glue later with series of 32-bit accesses on AArch32 side. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Родитель
328191c05e
Коммит
0968a61918
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@ -174,5 +174,19 @@ static inline void gic_write_bpr1(u32 val)
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#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
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#define gits_read_baser(c) readq_relaxed(c)
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#define gits_write_baser(v, c) writeq_relaxed(v, c)
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#define gits_read_cbaser(c) readq_relaxed(c)
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#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
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#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
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#define gicr_read_propbaser(c) readq_relaxed(c)
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#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
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#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
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#define gicr_read_pendbaser(c) readq_relaxed(c)
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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@ -835,7 +835,7 @@ static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
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{
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u32 idx = baser - its->tables;
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return readq_relaxed(its->base + GITS_BASER + (idx << 3));
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return gits_read_baser(its->base + GITS_BASER + (idx << 3));
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}
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static void its_write_baser(struct its_node *its, struct its_baser *baser,
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@ -843,7 +843,7 @@ static void its_write_baser(struct its_node *its, struct its_baser *baser,
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{
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u32 idx = baser - its->tables;
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writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
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gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
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baser->val = its_read_baser(its, baser);
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}
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@ -1125,8 +1125,8 @@ static void its_cpu_init_lpis(void)
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GICR_PROPBASER_WaWb |
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((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
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writeq_relaxed(val, rbase + GICR_PROPBASER);
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tmp = readq_relaxed(rbase + GICR_PROPBASER);
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gicr_write_propbaser(val, rbase + GICR_PROPBASER);
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tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
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if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
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if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
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@ -1138,7 +1138,7 @@ static void its_cpu_init_lpis(void)
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val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
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GICR_PROPBASER_CACHEABILITY_MASK);
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val |= GICR_PROPBASER_nC;
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writeq_relaxed(val, rbase + GICR_PROPBASER);
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gicr_write_propbaser(val, rbase + GICR_PROPBASER);
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}
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pr_info_once("GIC: using cache flushing for LPI property table\n");
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gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
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@ -1149,8 +1149,8 @@ static void its_cpu_init_lpis(void)
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GICR_PENDBASER_InnerShareable |
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GICR_PENDBASER_WaWb);
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writeq_relaxed(val, rbase + GICR_PENDBASER);
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tmp = readq_relaxed(rbase + GICR_PENDBASER);
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gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
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tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
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if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
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/*
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@ -1160,7 +1160,7 @@ static void its_cpu_init_lpis(void)
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val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
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GICR_PENDBASER_CACHEABILITY_MASK);
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val |= GICR_PENDBASER_nC;
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writeq_relaxed(val, rbase + GICR_PENDBASER);
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gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
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}
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/* Enable LPIs */
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@ -1716,8 +1716,8 @@ static int __init its_probe_one(struct resource *res,
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(ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
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GITS_CBASER_VALID);
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writeq_relaxed(baser, its->base + GITS_CBASER);
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tmp = readq_relaxed(its->base + GITS_CBASER);
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gits_write_cbaser(baser, its->base + GITS_CBASER);
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tmp = gits_read_cbaser(its->base + GITS_CBASER);
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if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
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if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
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@ -1729,13 +1729,13 @@ static int __init its_probe_one(struct resource *res,
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baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
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GITS_CBASER_CACHEABILITY_MASK);
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baser |= GITS_CBASER_nC;
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writeq_relaxed(baser, its->base + GITS_CBASER);
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gits_write_cbaser(baser, its->base + GITS_CBASER);
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}
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pr_info("ITS: using cache flushing for cmd queue\n");
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its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
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}
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writeq_relaxed(0, its->base + GITS_CWRITER);
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gits_write_cwriter(0, its->base + GITS_CWRITER);
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writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
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err = its_init_domain(handle, its);
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