Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle: - Properly setup irq handling for ATH79 platforms - Fix bootmem mapstart calculation for contiguous maps - Handle little endian and older CPUs correct in BPF - Fix console for Fulong 2E systems - Handle FTLB correctly on R6 CPUs - Fixes for CM, GIC and MAAR support code * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: Initialise MAARs on secondary CPUs MIPS: print MAAR configuration during boot MIPS: mm: compile maar_init unconditionally irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC. irqchip: mips-gic: Convert CPU numbers to VP IDs. MIPS: CM: Provide a function to map from CPU to VP ID. MIPS: Fix FTLB detection for R6 MIPS: cpu-features: Add cpu_has_ftlb MIPS: ATH79: Add irq chip ar7240-misc-intc MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip MIPS: BPF: Fix build on pre-R2 little endian CPUs MIPS: BPF: Avoid unreachable code on little endian MIPS: bootmem: Fix mapstart calculation for contiguous maps MIPS: Fix console output for Fulong2e system
This commit is contained in:
Linus Torvalds
Коммит
097f70b3c4
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@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority
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interrupt.
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Required Properties:
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- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
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as fallback
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- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
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"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
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- reg: Base address and size of the controllers memory area
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- interrupt-parent: phandle of the parent interrupt controller.
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- interrupts: Interrupt specifier for the controllers interrupt.
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@ -13,6 +13,9 @@ Required Properties:
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- #interrupt-cells : Specifies the number of cells needed to encode interrupt
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source, should be 1
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Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
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use ar7240 for all other SoCs.
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Please refer to interrupts.txt in this directory for details of the common
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Interrupt Controllers bindings used by client devices.
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@ -28,3 +31,16 @@ Example:
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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Another example:
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interrupt-controller@18060010 {
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compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
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reg = <0x18060010 0x4>;
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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@ -293,8 +293,26 @@ static int __init ath79_misc_intc_of_init(
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return 0;
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}
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IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
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ath79_misc_intc_of_init);
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static int __init ar7100_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
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ar7100_misc_intc_of_init);
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static int __init ar7240_misc_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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return ath79_misc_intc_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
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ar7240_misc_intc_of_init);
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static int __init ar79_cpu_intc_of_init(
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struct device_node *node, struct device_node *parent)
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@ -20,6 +20,9 @@
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#ifndef cpu_has_tlb
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#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
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#endif
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#ifndef cpu_has_ftlb
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#define cpu_has_ftlb (cpu_data[0].options & MIPS_CPU_FTLB)
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#endif
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#ifndef cpu_has_tlbinv
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#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
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#endif
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@ -385,6 +385,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
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#define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */
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#define MIPS_CPU_SP 0x10000000000ull /* Small (1KB) page support */
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#define MIPS_CPU_FTLB 0x20000000000ull /* CPU has Fixed-page-size TLB */
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/*
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* CPU ASE encodings
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@ -65,6 +65,15 @@ static inline void write_maar_pair(unsigned idx, phys_addr_t lower,
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back_to_back_c0_hazard();
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}
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/**
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* maar_init() - initialise MAARs
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*
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* Performs initialisation of MAARs for the current CPU, making use of the
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* platforms implementation of platform_maar_init where necessary and
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* duplicating the setup it provides on secondary CPUs.
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*/
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extern void maar_init(void);
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/**
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* struct maar_config - MAAR configuration data
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* @lower: The lowest address that the MAAR pair will affect. Must be
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@ -194,6 +194,7 @@ BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
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BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
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BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
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BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
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BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150)
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/* Core Local & Core Other register accessor functions */
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BUILD_CM_Cx_RW(reset_release, 0x00)
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@ -316,6 +317,10 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
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#define CM_GCR_L2_CONFIG_ASSOC_SHF 0
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#define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0)
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/* GCR_SYS_CONFIG2 register fields */
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#define CM_GCR_SYS_CONFIG2_MAXVPW_SHF 0
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#define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0)
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/* GCR_Cx_COHERENCE register fields */
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#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
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#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
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@ -405,4 +410,38 @@ static inline int mips_cm_revision(void)
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return read_gcr_rev();
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}
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/**
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* mips_cm_max_vp_width() - return the width in bits of VP indices
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*
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* Return: the width, in bits, of VP indices in fields that combine core & VP
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* indices.
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*/
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static inline unsigned int mips_cm_max_vp_width(void)
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{
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extern int smp_num_siblings;
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if (mips_cm_revision() >= CM_REV_CM3)
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return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
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return smp_num_siblings;
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}
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/**
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* mips_cm_vp_id() - calculate the hardware VP ID for a CPU
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* @cpu: the CPU whose VP ID to calculate
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*
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* Hardware such as the GIC uses identifiers for VPs which may not match the
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* CPU numbers used by Linux. This function calculates the hardware VP
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* identifier corresponding to a given CPU.
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*
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* Return: the VP ID for the CPU.
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*/
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static inline unsigned int mips_cm_vp_id(unsigned int cpu)
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{
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unsigned int core = cpu_data[cpu].core;
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unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
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return (core * mips_cm_max_vp_width()) + vp;
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}
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#endif /* __MIPS_ASM_MIPS_CM_H__ */
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@ -487,6 +487,8 @@
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/* Bits specific to the MIPS32/64 PRA. */
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#define MIPS_CONF_MT (_ULCAST_(7) << 7)
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#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
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#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
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#define MIPS_CONF_AR (_ULCAST_(7) << 10)
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#define MIPS_CONF_AT (_ULCAST_(3) << 13)
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#define MIPS_CONF_M (_ULCAST_(1) << 31)
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@ -410,16 +410,18 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
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static inline unsigned int decode_config0(struct cpuinfo_mips *c)
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{
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unsigned int config0;
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int isa;
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int isa, mt;
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config0 = read_c0_config();
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/*
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* Look for Standard TLB or Dual VTLB and FTLB
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*/
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if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
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(((config0 & MIPS_CONF_MT) >> 7) == 4))
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mt = config0 & MIPS_CONF_MT;
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if (mt == MIPS_CONF_MT_TLB)
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c->options |= MIPS_CPU_TLB;
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else if (mt == MIPS_CONF_MT_FTLB)
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c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
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isa = (config0 & MIPS_CONF_AT) >> 13;
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switch (isa) {
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@ -559,15 +561,18 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
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if (cpu_has_tlb) {
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if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
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c->options |= MIPS_CPU_TLBINV;
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/*
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* This is a bit ugly. R6 has dropped that field from
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* config4 and the only valid configuration is VTLB+FTLB so
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* set a good value for mmuextdef for that case.
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* R6 has dropped the MMUExtDef field from config4.
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* On R6 the fields always describe the FTLB, and only if it is
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* present according to Config.MT.
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*/
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if (cpu_has_mips_r6)
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if (!cpu_has_mips_r6)
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mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
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else if (cpu_has_ftlb)
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mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
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else
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mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
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mmuextdef = 0;
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switch (mmuextdef) {
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case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
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@ -338,7 +338,7 @@ static void __init bootmem_init(void)
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if (end <= reserved_end)
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continue;
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#ifdef CONFIG_BLK_DEV_INITRD
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/* mapstart should be after initrd_end */
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/* Skip zones before initrd and initrd itself */
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if (initrd_end && end <= (unsigned long)PFN_UP(__pa(initrd_end)))
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continue;
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#endif
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@ -371,6 +371,14 @@ static void __init bootmem_init(void)
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max_low_pfn = PFN_DOWN(HIGHMEM_START);
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}
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#ifdef CONFIG_BLK_DEV_INITRD
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/*
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* mapstart should be after initrd_end
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*/
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if (initrd_end)
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mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end)));
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#endif
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/*
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* Initialize the boot-time allocator with low memory only.
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*/
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@ -42,6 +42,7 @@
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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#include <asm/maar.h>
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cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
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@ -157,6 +158,7 @@ asmlinkage void start_secondary(void)
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mips_clockevent_init();
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mp_ops->init_secondary();
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cpu_report();
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maar_init();
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/*
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* XXX parity protection should be folded in here when it's converted
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|
|
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@ -64,6 +64,9 @@ void __init prom_init_env(void)
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}
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if (memsize == 0)
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memsize = 256;
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loongson_sysconf.nr_uarts = 1;
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pr_info("memsize=%u, highmemsize=%u\n", memsize, highmemsize);
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#else
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struct boot_params *boot_p;
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|
|
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@ -44,6 +44,7 @@
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/fixmap.h>
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#include <asm/maar.h>
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/*
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* We have up to 8 empty zeroed pages so we can map one of the right colour
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|
|
@ -252,6 +253,119 @@ void __init fixrange_init(unsigned long start, unsigned long end,
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#endif
|
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}
|
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|
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unsigned __weak platform_maar_init(unsigned num_pairs)
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{
|
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struct maar_config cfg[BOOT_MEM_MAP_MAX];
|
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unsigned i, num_configured, num_cfg = 0;
|
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phys_addr_t skip;
|
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|
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for (i = 0; i < boot_mem_map.nr_map; i++) {
|
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switch (boot_mem_map.map[i].type) {
|
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case BOOT_MEM_RAM:
|
||||
case BOOT_MEM_INIT_RAM:
|
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break;
|
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default:
|
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continue;
|
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}
|
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|
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skip = 0x10000 - (boot_mem_map.map[i].addr & 0xffff);
|
||||
|
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cfg[num_cfg].lower = boot_mem_map.map[i].addr;
|
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cfg[num_cfg].lower += skip;
|
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|
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cfg[num_cfg].upper = cfg[num_cfg].lower;
|
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cfg[num_cfg].upper += boot_mem_map.map[i].size - 1;
|
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cfg[num_cfg].upper -= skip;
|
||||
|
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cfg[num_cfg].attrs = MIPS_MAAR_S;
|
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num_cfg++;
|
||||
}
|
||||
|
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num_configured = maar_config(cfg, num_cfg, num_pairs);
|
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if (num_configured < num_cfg)
|
||||
pr_warn("Not enough MAAR pairs (%u) for all bootmem regions (%u)\n",
|
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num_pairs, num_cfg);
|
||||
|
||||
return num_configured;
|
||||
}
|
||||
|
||||
void maar_init(void)
|
||||
{
|
||||
unsigned num_maars, used, i;
|
||||
phys_addr_t lower, upper, attr;
|
||||
static struct {
|
||||
struct maar_config cfgs[3];
|
||||
unsigned used;
|
||||
} recorded = { { { 0 } }, 0 };
|
||||
|
||||
if (!cpu_has_maar)
|
||||
return;
|
||||
|
||||
/* Detect the number of MAARs */
|
||||
write_c0_maari(~0);
|
||||
back_to_back_c0_hazard();
|
||||
num_maars = read_c0_maari() + 1;
|
||||
|
||||
/* MAARs should be in pairs */
|
||||
WARN_ON(num_maars % 2);
|
||||
|
||||
/* Set MAARs using values we recorded already */
|
||||
if (recorded.used) {
|
||||
used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
|
||||
BUG_ON(used != recorded.used);
|
||||
} else {
|
||||
/* Configure the required MAARs */
|
||||
used = platform_maar_init(num_maars / 2);
|
||||
}
|
||||
|
||||
/* Disable any further MAARs */
|
||||
for (i = (used * 2); i < num_maars; i++) {
|
||||
write_c0_maari(i);
|
||||
back_to_back_c0_hazard();
|
||||
write_c0_maar(0);
|
||||
back_to_back_c0_hazard();
|
||||
}
|
||||
|
||||
if (recorded.used)
|
||||
return;
|
||||
|
||||
pr_info("MAAR configuration:\n");
|
||||
for (i = 0; i < num_maars; i += 2) {
|
||||
write_c0_maari(i);
|
||||
back_to_back_c0_hazard();
|
||||
upper = read_c0_maar();
|
||||
|
||||
write_c0_maari(i + 1);
|
||||
back_to_back_c0_hazard();
|
||||
lower = read_c0_maar();
|
||||
|
||||
attr = lower & upper;
|
||||
lower = (lower & MIPS_MAAR_ADDR) << 4;
|
||||
upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
|
||||
|
||||
pr_info(" [%d]: ", i / 2);
|
||||
if (!(attr & MIPS_MAAR_V)) {
|
||||
pr_cont("disabled\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
pr_cont("%pa-%pa", &lower, &upper);
|
||||
|
||||
if (attr & MIPS_MAAR_S)
|
||||
pr_cont(" speculate");
|
||||
|
||||
pr_cont("\n");
|
||||
|
||||
/* Record the setup for use on secondary CPUs */
|
||||
if (used <= ARRAY_SIZE(recorded.cfgs)) {
|
||||
recorded.cfgs[recorded.used].lower = lower;
|
||||
recorded.cfgs[recorded.used].upper = upper;
|
||||
recorded.cfgs[recorded.used].attrs = attr;
|
||||
recorded.used++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NEED_MULTIPLE_NODES
|
||||
int page_is_ram(unsigned long pagenr)
|
||||
{
|
||||
|
|
@ -334,69 +448,6 @@ static inline void mem_init_free_highmem(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
unsigned __weak platform_maar_init(unsigned num_pairs)
|
||||
{
|
||||
struct maar_config cfg[BOOT_MEM_MAP_MAX];
|
||||
unsigned i, num_configured, num_cfg = 0;
|
||||
phys_addr_t skip;
|
||||
|
||||
for (i = 0; i < boot_mem_map.nr_map; i++) {
|
||||
switch (boot_mem_map.map[i].type) {
|
||||
case BOOT_MEM_RAM:
|
||||
case BOOT_MEM_INIT_RAM:
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
skip = 0x10000 - (boot_mem_map.map[i].addr & 0xffff);
|
||||
|
||||
cfg[num_cfg].lower = boot_mem_map.map[i].addr;
|
||||
cfg[num_cfg].lower += skip;
|
||||
|
||||
cfg[num_cfg].upper = cfg[num_cfg].lower;
|
||||
cfg[num_cfg].upper += boot_mem_map.map[i].size - 1;
|
||||
cfg[num_cfg].upper -= skip;
|
||||
|
||||
cfg[num_cfg].attrs = MIPS_MAAR_S;
|
||||
num_cfg++;
|
||||
}
|
||||
|
||||
num_configured = maar_config(cfg, num_cfg, num_pairs);
|
||||
if (num_configured < num_cfg)
|
||||
pr_warn("Not enough MAAR pairs (%u) for all bootmem regions (%u)\n",
|
||||
num_pairs, num_cfg);
|
||||
|
||||
return num_configured;
|
||||
}
|
||||
|
||||
static void maar_init(void)
|
||||
{
|
||||
unsigned num_maars, used, i;
|
||||
|
||||
if (!cpu_has_maar)
|
||||
return;
|
||||
|
||||
/* Detect the number of MAARs */
|
||||
write_c0_maari(~0);
|
||||
back_to_back_c0_hazard();
|
||||
num_maars = read_c0_maari() + 1;
|
||||
|
||||
/* MAARs should be in pairs */
|
||||
WARN_ON(num_maars % 2);
|
||||
|
||||
/* Configure the required MAARs */
|
||||
used = platform_maar_init(num_maars / 2);
|
||||
|
||||
/* Disable any further MAARs */
|
||||
for (i = (used * 2); i < num_maars; i++) {
|
||||
write_c0_maari(i);
|
||||
back_to_back_c0_hazard();
|
||||
write_c0_maar(0);
|
||||
back_to_back_c0_hazard();
|
||||
}
|
||||
}
|
||||
|
||||
void __init mem_init(void)
|
||||
{
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
|
|
|
|||
|
|
@ -64,8 +64,20 @@ sk_load_word_positive:
|
|||
PTR_ADDU t1, $r_skb_data, offset
|
||||
lw $r_A, 0(t1)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
wsbh t0, $r_A
|
||||
rotr $r_A, t0, 16
|
||||
# else
|
||||
sll t0, $r_A, 24
|
||||
srl t1, $r_A, 24
|
||||
srl t2, $r_A, 8
|
||||
or t0, t0, t1
|
||||
andi t2, t2, 0xff00
|
||||
andi t1, $r_A, 0xff00
|
||||
or t0, t0, t2
|
||||
sll t1, t1, 8
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#endif
|
||||
jr $r_ra
|
||||
move $r_ret, zero
|
||||
|
|
@ -80,8 +92,16 @@ sk_load_half_positive:
|
|||
PTR_ADDU t1, $r_skb_data, offset
|
||||
lh $r_A, 0(t1)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
wsbh t0, $r_A
|
||||
seh $r_A, t0
|
||||
# else
|
||||
sll t0, $r_A, 24
|
||||
andi t1, $r_A, 0xff00
|
||||
sra t0, t0, 16
|
||||
srl t1, t1, 8
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#endif
|
||||
jr $r_ra
|
||||
move $r_ret, zero
|
||||
|
|
@ -148,23 +168,47 @@ sk_load_byte_positive:
|
|||
NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(4)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
wsbh t0, $r_s0
|
||||
jr $r_ra
|
||||
rotr $r_A, t0, 16
|
||||
#endif
|
||||
# else
|
||||
sll t0, $r_s0, 24
|
||||
srl t1, $r_s0, 24
|
||||
srl t2, $r_s0, 8
|
||||
or t0, t0, t1
|
||||
andi t2, t2, 0xff00
|
||||
andi t1, $r_s0, 0xff00
|
||||
or t0, t0, t2
|
||||
sll t1, t1, 8
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#else
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
#endif
|
||||
|
||||
END(bpf_slow_path_word)
|
||||
|
||||
NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)
|
||||
bpf_slow_path_common(2)
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
|
||||
jr $r_ra
|
||||
wsbh $r_A, $r_s0
|
||||
#endif
|
||||
# else
|
||||
sll t0, $r_s0, 8
|
||||
andi t1, $r_s0, 0xff00
|
||||
andi t0, t0, 0xff00
|
||||
srl t1, t1, 8
|
||||
jr $r_ra
|
||||
or $r_A, t0, t1
|
||||
# endif
|
||||
#else
|
||||
jr $r_ra
|
||||
move $r_A, $r_s0
|
||||
#endif
|
||||
|
||||
END(bpf_slow_path_half)
|
||||
|
||||
|
|
|
|||
|
|
@ -320,6 +320,14 @@ static void gic_handle_shared_int(bool chained)
|
|||
intrmask[i] = gic_read(intrmask_reg);
|
||||
pending_reg += gic_reg_step;
|
||||
intrmask_reg += gic_reg_step;
|
||||
|
||||
if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
|
||||
continue;
|
||||
|
||||
pending[i] |= (u64)gic_read(pending_reg) << 32;
|
||||
intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
|
||||
pending_reg += gic_reg_step;
|
||||
intrmask_reg += gic_reg_step;
|
||||
}
|
||||
|
||||
bitmap_and(pending, pending, intrmask, gic_shared_intrs);
|
||||
|
|
@ -426,7 +434,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
|
|||
spin_lock_irqsave(&gic_lock, flags);
|
||||
|
||||
/* Re-route this IRQ */
|
||||
gic_map_to_vpe(irq, cpumask_first(&tmp));
|
||||
gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
|
||||
|
||||
/* Update the pcpu_masks */
|
||||
for (i = 0; i < NR_CPUS; i++)
|
||||
|
|
@ -599,7 +607,7 @@ static __init void gic_ipi_init_one(unsigned int intr, int cpu,
|
|||
GIC_SHARED_TO_HWIRQ(intr));
|
||||
int i;
|
||||
|
||||
gic_map_to_vpe(intr, cpu);
|
||||
gic_map_to_vpe(intr, mips_cm_vp_id(cpu));
|
||||
for (i = 0; i < NR_CPUS; i++)
|
||||
clear_bit(intr, pcpu_masks[i].pcpu_mask);
|
||||
set_bit(intr, pcpu_masks[cpu].pcpu_mask);
|
||||
|
|
|
|||
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