Visconti5 SoC changes for v5.10 (take two)
- Add dt-bindings for Toshiba Visconti ARM SoCs - Add dt-bindings for the TMPV7708 RM main board - Add initial support for Toshiba Visconti platform - Add device tree for TMPV7708 RM main board - Add information for Toshiba Visconti ARM SoCs to MAINTAINERS - Enable configs for Toshiba Visconti to arm64's defconfig -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEXmKe5SMhlzV7hM9DMiR/u0CtH6YFAl9rBdkACgkQMiR/u0Ct H6bECxAAkoXu7alw5LqfyDkiOHKehMoKjLXYdIHANFii4+K/H+rkkwPoQS96rOPM N2rvXP4ddtbZto/gtiUk4rGBUFN/onH0uAVnewgspORKiV1fZSfJtOel+s5wZFmR YNpvPTlxnY2qh+fgf1RJdNdfI8Bg9ebKgPnO9m8gZO5lGBEAQCAkTALH+RoBb/Y0 j/2/ZcGEb3A6V3tJu+lQNERdWurHhUAcdZ5q/N86APPe0TWf0zNOMeLc2cbeGihZ fRv9vbhZfO3b0XuEjYw2I5qAo80cubU/1m5z+YYzJFj1FBUKDHfcaVZevBvJu7Aa xvnb0MfAypw2zNpvdZEZw8iCNUEaWxgxwqsbFpr67eg4MXe2b8AFSS4oU1WGd07K Rnc24yG2r+AeRa8J+AYKTTDtpLOyogDWXSqba/GavbMQQ8VyTEt0e792fH5u8tCk MtCA3thXbNaRA3d8wL9S/RnGMyiXKoZqjRGBrdgSVGubw5qs6eNz/ZDH1ufoBBVA BEyrIXwBI4qg6j+Z+Bfr/e+MMOP5pcVEoFiGaVK0RMTTf4/F1PnVvk7yO9KN+LaA uRcUyh1OGKPh+7bPt6o2DGpq3sHiEPCH3y/TULhmbFP0GcOYcxGC6vddvSq4CGyb IcISu3JawgpL6h1W7HaSeK2ugPrutwgRagy0XlOiJOHVfT5HWas= =RVbA -----END PGP SIGNATURE----- Merge tag 'visconti-initial-for-5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti into arm/dt Visconti5 SoC changes for v5.10 (take two) - Add dt-bindings for Toshiba Visconti ARM SoCs - Add dt-bindings for the TMPV7708 RM main board - Add initial support for Toshiba Visconti platform - Add device tree for TMPV7708 RM main board - Add information for Toshiba Visconti ARM SoCs to MAINTAINERS - Enable configs for Toshiba Visconti to arm64's defconfig * tag 'visconti-initial-for-5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti: arm64: defconfig: Enable configs for Toshiba Visconti MAINTAINERS: Add information for Toshiba Visconti ARM SoCs arm64: dts: visconti: Add device tree for TMPV7708 RM main board arm64: visconti: Add initial support for Toshiba Visconti platform dt-bindings: arm: toshiba: Add the TMPV7708 RM main board dt-bindings: arm: toshiba: add Toshiba Visconti ARM SoCs Link: https://lore.kernel.org/r/20200923085236.4hu53gmnnmqkttuy@toshiba.co.jp Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
098bfcec1b
|
|
@ -0,0 +1,22 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/toshiba.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Toshiba Visconti Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Visconti5 TMPV7708
|
||||
items:
|
||||
- enum:
|
||||
- toshiba,tmpv7708-rm-mbrc # TMPV7708 RM main board
|
||||
- const: toshiba,tmpv7708
|
||||
...
|
||||
11
MAINTAINERS
11
MAINTAINERS
|
|
@ -2650,6 +2650,17 @@ M: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
|
|||
M: Dirk Opfer <dirk@opfer-online.de>
|
||||
S: Maintained
|
||||
|
||||
ARM/TOSHIBA VISCONTI ARCHITECTURE
|
||||
M: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
|
||||
F: Documentation/devicetree/bindings/arm/toshiba.yaml
|
||||
F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml
|
||||
F: arch/arm64/boot/dts/toshiba/
|
||||
F: drivers/pinctrl/visconti/
|
||||
N: visconti
|
||||
|
||||
ARM/UNIPHIER ARCHITECTURE
|
||||
M: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
|
|||
|
|
@ -300,6 +300,13 @@ config ARCH_VEXPRESS
|
|||
This enables support for the ARMv8 software model (Versatile
|
||||
Express).
|
||||
|
||||
config ARCH_VISCONTI
|
||||
bool "Toshiba Visconti SoC Family"
|
||||
select PINCTRL
|
||||
select PINCTRL_VISCONTI
|
||||
help
|
||||
This enables support for Toshiba Visconti SoCs Family.
|
||||
|
||||
config ARCH_VULCAN
|
||||
def_bool n
|
||||
|
||||
|
|
|
|||
|
|
@ -27,5 +27,6 @@ subdir-y += socionext
|
|||
subdir-y += sprd
|
||||
subdir-y += synaptics
|
||||
subdir-y += ti
|
||||
subdir-y += toshiba
|
||||
subdir-y += xilinx
|
||||
subdir-y += zte
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
dtb-$(CONFIG_ARCH_VISCONTI) += tmpv7708-rm-mbrc.dtb
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree File for TMPV7708 RM main board
|
||||
*
|
||||
* (C) Copyright 2020, Toshiba Corporation.
|
||||
* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "tmpv7708.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toshiba TMPV7708 RM main board";
|
||||
compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
/* 768MB memory */
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x30000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
clocks = <&uart_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Source for the TMPV7708
|
||||
*
|
||||
* (C) Copyright 2018 - 2020, Toshiba Corporation.
|
||||
* (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
|
||||
|
||||
/ {
|
||||
compatible = "toshiba,tmpv7708";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x00>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x01>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x02>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x03>;
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x101>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x102>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
compatible = "arm,cortex-a53";
|
||||
device_type = "cpu";
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0x0 0x81100000>;
|
||||
reg = <0x103>;
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts =
|
||||
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <150000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@24001000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
reg = <0 0x24001000 0 0x1000>,
|
||||
<0 0x24002000 0 0x2000>,
|
||||
<0 0x24004000 0 0x2000>,
|
||||
<0 0x24006000 0 0x2000>;
|
||||
};
|
||||
|
||||
pmux: pmux@24190000 {
|
||||
compatible = "toshiba,tmpv7708-pinctrl";
|
||||
reg = <0 0x24190000 0 0x10000>;
|
||||
};
|
||||
|
||||
uart0: serial@28200000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0x28200000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@28201000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0x28201000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@28202000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0x28202000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@28203000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0 0x28203000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@28030000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28030000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@28031000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28031000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@28032000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28032000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@28033000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28033000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@28034000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28034000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@28035000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28035000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@28036000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28036000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@28037000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28037000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@28038000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0 0x28038000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c8_pins>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@28140000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28140000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@28141000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28141000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@28142000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28142000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@28143000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28143000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi3_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@28144000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28144000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi4_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi5: spi@28145000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28145000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi5_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@28146000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0 0x28146000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi6_pins>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "tmpv7708_pins.dtsi"
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
&pmux {
|
||||
spi0_pins: spi0-pins {
|
||||
function = "spi0";
|
||||
groups = "spi0_grp";
|
||||
};
|
||||
spi1_pins: spi1-pins {
|
||||
function = "spi1";
|
||||
groups = "spi1_grp";
|
||||
};
|
||||
spi2_pins: spi2-pins {
|
||||
function = "spi2";
|
||||
groups = "spi2_grp";
|
||||
};
|
||||
spi3_pins: spi3-pins {
|
||||
function = "spi3";
|
||||
groups = "spi3_grp";
|
||||
};
|
||||
spi4_pins: spi4-pins {
|
||||
function = "spi4";
|
||||
groups = "spi4_grp";
|
||||
};
|
||||
spi5_pins: spi5-pins {
|
||||
function = "spi5";
|
||||
groups = "spi5_grp";
|
||||
};
|
||||
spi6_pins: spi6-pins {
|
||||
function = "spi6";
|
||||
groups = "spi6_grp";
|
||||
};
|
||||
uart0_pins: uart0-pins {
|
||||
function = "uart0";
|
||||
groups = "uart0_grp";
|
||||
};
|
||||
uart1_pins: uart1-pins {
|
||||
function = "uart1";
|
||||
groups = "uart1_grp";
|
||||
};
|
||||
uart2_pins: uart2-pins {
|
||||
function = "uart2";
|
||||
groups = "uart2_grp";
|
||||
};
|
||||
uart3_pins: uart3-pins {
|
||||
function = "uart3";
|
||||
groups = "uart3_grp";
|
||||
};
|
||||
i2c0_pins: i2c0-pins {
|
||||
function = "i2c0";
|
||||
groups = "i2c0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c1_pins: i2c1-pins {
|
||||
function = "i2c1";
|
||||
groups = "i2c1_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c2_pins: i2c2-pins {
|
||||
function = "i2c2";
|
||||
groups = "i2c2_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c3_pins: i2c3-pins {
|
||||
function = "i2c3";
|
||||
groups = "i2c3_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c4_pins: i2c4-pins {
|
||||
function = "i2c4";
|
||||
groups = "i2c4_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c5_pins: i2c5-pins {
|
||||
function = "i2c5";
|
||||
groups = "i2c5_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c6_pins: i2c6-pins {
|
||||
function = "i2c6";
|
||||
groups = "i2c6_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c7_pins: i2c7-pins {
|
||||
function = "i2c7";
|
||||
groups = "i2c7_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
i2c8_pins: i2c8-pins {
|
||||
function = "i2c8";
|
||||
groups = "i2c8_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
|
@ -57,6 +57,7 @@ CONFIG_ARCH_THUNDER=y
|
|||
CONFIG_ARCH_THUNDER2=y
|
||||
CONFIG_ARCH_UNIPHIER=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
CONFIG_ARCH_VISCONTI=y
|
||||
CONFIG_ARCH_XGENE=y
|
||||
CONFIG_ARCH_ZX=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче