sh: hw-breakpoints: Add preliminary support for SH-4A UBC.
This adds preliminary support for the SH-4A UBC to the hw-breakpoints API. Presently only a single channel is implemented, and the ptrace interface still needs to be converted. This is the first step to cleaning up the long-standing UBC mess, making the UBC more generally accessible, and finally making it SMP safe. An additional abstraction will be layered on top of this as with the perf events code to permit the various CPU families to wire up support for their own specific UBCs, as many variations exist. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
6ec22f9b03
Коммит
09a0729477
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@ -39,6 +39,7 @@ config SUPERH32
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select HAVE_FUNCTION_TRACE_MCOUNT_TEST
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select HAVE_FUNCTION_GRAPH_TRACER
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select HAVE_ARCH_KGDB
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select HAVE_HW_BREAKPOINT if CPU_SH4A
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select ARCH_HIBERNATION_POSSIBLE if MMU
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config SUPERH64
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@ -1,6 +1,8 @@
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include include/asm-generic/Kbuild.asm
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header-y += cachectl.h cpu-features.h
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header-y += cachectl.h
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header-y += cpu-features.h
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header-y += hw_breakpoint.h
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unifdef-y += unistd_32.h
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unifdef-y += unistd_64.h
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@ -0,0 +1,53 @@
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#ifndef __ASM_SH_HW_BREAKPOINT_H
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#define __ASM_SH_HW_BREAKPOINT_H
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#include <linux/kdebug.h>
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#include <linux/types.h>
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#include <asm/ubc.h>
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#ifdef __KERNEL__
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#define __ARCH_HW_BREAKPOINT_H
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struct arch_hw_breakpoint {
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char *name; /* Contains name of the symbol to set bkpt */
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unsigned long address;
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unsigned long asid;
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u16 len;
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u16 type;
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};
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enum {
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SH_BREAKPOINT_READ = (1 << 1),
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SH_BREAKPOINT_WRITE = (1 << 2),
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SH_BREAKPOINT_RW = SH_BREAKPOINT_READ | SH_BREAKPOINT_WRITE,
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SH_BREAKPOINT_LEN_1 = (1 << 12),
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SH_BREAKPOINT_LEN_2 = (1 << 13),
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SH_BREAKPOINT_LEN_4 = SH_BREAKPOINT_LEN_1 | SH_BREAKPOINT_LEN_2,
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SH_BREAKPOINT_LEN_8 = (1 << 14),
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};
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/* Total number of available UBC channels */
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#define HBP_NUM 1 /* XXX */
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struct perf_event;
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struct task_struct;
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struct pmu;
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extern int arch_check_va_in_userspace(unsigned long va, u16 hbp_len);
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extern int arch_validate_hwbkpt_settings(struct perf_event *bp,
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struct task_struct *tsk);
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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int arch_install_hw_breakpoint(struct perf_event *bp);
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void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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void hw_breakpoint_pmu_read(struct perf_event *bp);
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void hw_breakpoint_pmu_unthrottle(struct perf_event *bp);
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extern void arch_fill_perf_breakpoint(struct perf_event *bp);
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extern struct pmu perf_ops_bp;
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_HW_BREAKPOINT_H */
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@ -6,6 +6,8 @@ enum die_val {
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DIE_TRAP,
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DIE_NMI,
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DIE_OOPS,
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DIE_BREAKPOINT,
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DIE_SSTEP,
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};
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#endif /* __ASM_SH_KDEBUG_H */
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@ -14,6 +14,7 @@
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#include <asm/ubc.h>
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/*
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* Default implementation of macro that returns current
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@ -99,8 +100,8 @@ struct thread_struct {
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unsigned long sp;
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unsigned long pc;
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/* Hardware debugging registers */
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unsigned long ubc_pc;
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/* Save middle states of ptrace breakpoints */
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struct perf_event *ptrace_bps[NR_UBC_CHANNELS];
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/* floating point info */
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union sh_fpu_union fpu;
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@ -111,9 +112,6 @@ struct thread_struct {
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#endif
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};
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/* Count of active tasks with UBC settings */
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extern int ubc_usercnt;
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#define INIT_THREAD { \
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.sp = sizeof(init_stack) + (long) &init_stack, \
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}
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@ -144,8 +144,6 @@ void per_cpu_trap_init(void);
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void default_idle(void);
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void cpu_idle_wait(void);
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asmlinkage void break_point_trap(void);
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#ifdef CONFIG_SUPERH32
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#define BUILD_TRAP_HANDLER(name) \
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asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
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@ -117,6 +117,7 @@ extern void free_thread_info(struct thread_info *ti);
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#define TIF_SECCOMP 6 /* secure computing */
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#define TIF_NOTIFY_RESUME 7 /* callback before returning to user */
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#define TIF_SYSCALL_TRACEPOINT 8 /* for ftrace syscall instrumentation */
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#define TIF_DEBUG 9 /* uses UBC */
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#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
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#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
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#define TIF_MEMDIE 18
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@ -131,6 +132,7 @@ extern void free_thread_info(struct thread_info *ti);
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#define _TIF_SECCOMP (1 << TIF_SECCOMP)
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#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
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#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
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#define _TIF_DEBUG (1 << TIF_DEBUG)
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#define _TIF_USEDFPU (1 << TIF_USEDFPU)
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#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
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#define _TIF_FREEZE (1 << TIF_FREEZE)
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@ -10,8 +10,8 @@
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*/
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#ifndef __ASM_SH_UBC_H
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#define __ASM_SH_UBC_H
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#ifdef __KERNEL__
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#ifdef __KERNEL__
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#include <cpu/ubc.h>
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/* User Break Controller */
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@ -60,6 +60,12 @@
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#define BRCR_UBDE (1 << 0)
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#endif
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/*
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* All SH parts have 2 UBC channels. I defy any hardware designer to
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* invalidate this assertion.
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*/
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#define NR_UBC_CHANNELS 2
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#ifndef __ASSEMBLY__
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/* arch/sh/kernel/cpu/ubc.S */
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extern void ubc_sleep(void);
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@ -36,6 +36,7 @@ obj-$(CONFIG_DUMP_CODE) += disassemble.o
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obj-$(CONFIG_HIBERNATION) += swsusp.o
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obj-$(CONFIG_DWARF_UNWINDER) += dwarf.o
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
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EXTRA_CFLAGS += -Werror
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@ -49,7 +49,7 @@ ENTRY(exception_handling_table)
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.long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
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.long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
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.long nmi_trap_handler /* 1C0 */ ! Allow trap to debugger
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.long break_point_trap /* 1E0 */
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.long breakpoint_trap_handler /* 1E0 */
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/*
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* Pad the remainder of the table out, exceptions residing in far
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@ -0,0 +1,416 @@
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/*
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* arch/sh/kernel/hw_breakpoint.c
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*
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* Unified kernel/user-space hardware breakpoint facility for the on-chip UBC.
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*
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/perf_event.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/percpu.h>
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#include <linux/kallsyms.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/kdebug.h>
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#include <linux/io.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/mmu_context.h>
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struct ubc_context {
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unsigned long pc;
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unsigned long state;
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};
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/* Per cpu ubc channel state */
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static DEFINE_PER_CPU(struct ubc_context, ubc_ctx[HBP_NUM]);
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/*
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* Stores the breakpoints currently in use on each breakpoint address
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* register for each cpus
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*/
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
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static int __init ubc_init(void)
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{
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__raw_writel(0, UBC_CAMR0);
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__raw_writel(0, UBC_CBR0);
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__raw_writel(0, UBC_CBCR);
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__raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR0);
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/* dummy read for write posting */
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(void)__raw_readl(UBC_CRR0);
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return 0;
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}
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arch_initcall(ubc_init);
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/*
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* Install a perf counter breakpoint.
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*
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* We seek a free UBC channel and use it for this breakpoint.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct ubc_context *ubc_ctx;
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int i;
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for (i = 0; i < HBP_NUM; i++) {
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struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
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if (!*slot) {
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*slot = bp;
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break;
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}
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}
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if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
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return -EBUSY;
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ubc_ctx = &__get_cpu_var(ubc_ctx[i]);
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ubc_ctx->pc = info->address;
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ubc_ctx->state = info->len | info->type;
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__raw_writel(UBC_CBR_CE | ubc_ctx->state, UBC_CBR0);
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__raw_writel(ubc_ctx->pc, UBC_CAR0);
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return 0;
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}
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/*
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* Uninstall the breakpoint contained in the given counter.
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*
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* First we search the debug address register it uses and then we disable
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* it.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct ubc_context *ubc_ctx;
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int i;
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for (i = 0; i < HBP_NUM; i++) {
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struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
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if (*slot == bp) {
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*slot = NULL;
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break;
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}
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}
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if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
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return;
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ubc_ctx = &__get_cpu_var(ubc_ctx[i]);
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ubc_ctx->pc = 0;
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ubc_ctx->state &= ~(info->len | info->type);
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__raw_writel(ubc_ctx->pc, UBC_CBR0);
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__raw_writel(ubc_ctx->state, UBC_CAR0);
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}
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static int get_hbp_len(u16 hbp_len)
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{
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unsigned int len_in_bytes = 0;
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switch (hbp_len) {
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case SH_BREAKPOINT_LEN_1:
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len_in_bytes = 1;
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break;
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case SH_BREAKPOINT_LEN_2:
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len_in_bytes = 2;
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break;
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case SH_BREAKPOINT_LEN_4:
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len_in_bytes = 4;
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break;
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case SH_BREAKPOINT_LEN_8:
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len_in_bytes = 8;
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break;
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}
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return len_in_bytes;
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}
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/*
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* Check for virtual address in user space.
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*/
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int arch_check_va_in_userspace(unsigned long va, u16 hbp_len)
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{
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unsigned int len;
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len = get_hbp_len(hbp_len);
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return (va <= TASK_SIZE - len);
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}
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/*
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* Check for virtual address in kernel space.
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*/
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static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
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{
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unsigned int len;
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len = get_hbp_len(hbp_len);
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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/*
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* Store a breakpoint's encoded address, length, and type.
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*/
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static int arch_store_info(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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/*
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* User-space requests will always have the address field populated
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* For kernel-addresses, either the address or symbol name can be
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* specified.
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*/
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if (info->name)
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info->address = (unsigned long)kallsyms_lookup_name(info->name);
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if (info->address) {
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info->asid = get_asid();
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return 0;
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}
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return -EINVAL;
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}
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int arch_bp_generic_fields(int sh_len, int sh_type,
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int *gen_len, int *gen_type)
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{
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/* Len */
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switch (sh_len) {
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case SH_BREAKPOINT_LEN_1:
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*gen_len = HW_BREAKPOINT_LEN_1;
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break;
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case SH_BREAKPOINT_LEN_2:
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*gen_len = HW_BREAKPOINT_LEN_2;
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break;
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case SH_BREAKPOINT_LEN_4:
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*gen_len = HW_BREAKPOINT_LEN_4;
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break;
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case SH_BREAKPOINT_LEN_8:
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*gen_len = HW_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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/* Type */
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switch (sh_type) {
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case SH_BREAKPOINT_READ:
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*gen_type = HW_BREAKPOINT_R;
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case SH_BREAKPOINT_WRITE:
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*gen_type = HW_BREAKPOINT_W;
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break;
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case SH_BREAKPOINT_RW:
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*gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int arch_build_bp_info(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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info->address = bp->attr.bp_addr;
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/* Len */
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switch (bp->attr.bp_len) {
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case HW_BREAKPOINT_LEN_1:
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info->len = SH_BREAKPOINT_LEN_1;
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break;
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case HW_BREAKPOINT_LEN_2:
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info->len = SH_BREAKPOINT_LEN_2;
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break;
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case HW_BREAKPOINT_LEN_4:
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info->len = SH_BREAKPOINT_LEN_4;
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break;
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case HW_BREAKPOINT_LEN_8:
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info->len = SH_BREAKPOINT_LEN_8;
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break;
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default:
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return -EINVAL;
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}
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/* Type */
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switch (bp->attr.bp_type) {
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case HW_BREAKPOINT_R:
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info->type = SH_BREAKPOINT_READ;
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break;
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case HW_BREAKPOINT_W:
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info->type = SH_BREAKPOINT_WRITE;
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break;
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case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
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info->type = SH_BREAKPOINT_RW;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings
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*/
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int arch_validate_hwbkpt_settings(struct perf_event *bp,
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struct task_struct *tsk)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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unsigned int align;
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int ret;
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ret = arch_build_bp_info(bp);
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if (ret)
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return ret;
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ret = -EINVAL;
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switch (info->len) {
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||||
case SH_BREAKPOINT_LEN_1:
|
||||
align = 0;
|
||||
break;
|
||||
case SH_BREAKPOINT_LEN_2:
|
||||
align = 1;
|
||||
break;
|
||||
case SH_BREAKPOINT_LEN_4:
|
||||
align = 3;
|
||||
break;
|
||||
case SH_BREAKPOINT_LEN_8:
|
||||
align = 7;
|
||||
break;
|
||||
default:
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (bp->callback)
|
||||
ret = arch_store_info(bp);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Check that the low-order bits of the address are appropriate
|
||||
* for the alignment implied by len.
|
||||
*/
|
||||
if (info->address & align)
|
||||
return -EINVAL;
|
||||
|
||||
/* Check that the virtual address is in the proper range */
|
||||
if (tsk) {
|
||||
if (!arch_check_va_in_userspace(info->address, info->len))
|
||||
return -EFAULT;
|
||||
} else {
|
||||
if (!arch_check_va_in_kernelspace(info->address, info->len))
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Release the user breakpoints used by ptrace
|
||||
*/
|
||||
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
|
||||
{
|
||||
int i;
|
||||
struct thread_struct *t = &tsk->thread;
|
||||
|
||||
for (i = 0; i < HBP_NUM; i++) {
|
||||
unregister_hw_breakpoint(t->ptrace_bps[i]);
|
||||
t->ptrace_bps[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int __kprobes hw_breakpoint_handler(struct die_args *args)
|
||||
{
|
||||
int cpu, i, rc = NOTIFY_STOP;
|
||||
struct perf_event *bp;
|
||||
unsigned long val;
|
||||
|
||||
val = __raw_readl(UBC_CBR0);
|
||||
__raw_writel(val & ~UBC_CBR_CE, UBC_CBR0);
|
||||
|
||||
cpu = get_cpu();
|
||||
for (i = 0; i < HBP_NUM; i++) {
|
||||
/*
|
||||
* The counter may be concurrently released but that can only
|
||||
* occur from a call_rcu() path. We can then safely fetch
|
||||
* the breakpoint, use its callback, touch its counter
|
||||
* while we are in an rcu_read_lock() path.
|
||||
*/
|
||||
rcu_read_lock();
|
||||
|
||||
bp = per_cpu(bp_per_reg[i], cpu);
|
||||
if (bp) {
|
||||
rc = NOTIFY_DONE;
|
||||
} else {
|
||||
rcu_read_unlock();
|
||||
break;
|
||||
}
|
||||
|
||||
(bp->callback)(bp, args->regs);
|
||||
|
||||
rcu_read_unlock();
|
||||
}
|
||||
|
||||
if (bp) {
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
|
||||
__raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR0);
|
||||
__raw_writel(info->address, UBC_CAR0);
|
||||
}
|
||||
|
||||
put_cpu();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(breakpoint)
|
||||
{
|
||||
unsigned long ex = lookup_exception_vector();
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
notify_die(DIE_BREAKPOINT, "breakpoint", regs, 0, ex, SIGTRAP);
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle debug exception notifications.
|
||||
*/
|
||||
int __kprobes hw_breakpoint_exceptions_notify(struct notifier_block *unused,
|
||||
unsigned long val, void *data)
|
||||
{
|
||||
if (val != DIE_BREAKPOINT)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
return hw_breakpoint_handler(data);
|
||||
}
|
||||
|
||||
void hw_breakpoint_pmu_read(struct perf_event *bp)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void hw_breakpoint_pmu_unthrottle(struct perf_event *bp)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/fs.h>
|
||||
#include <linux/ftrace.h>
|
||||
#include <linux/preempt.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgalloc.h>
|
||||
|
|
@ -34,8 +35,6 @@
|
|||
#include <asm/syscalls.h>
|
||||
#include <asm/watchdog.h>
|
||||
|
||||
int ubc_usercnt = 0;
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
static void watchdog_trigger_immediate(void)
|
||||
{
|
||||
|
|
@ -148,16 +147,15 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
|
|||
*/
|
||||
void exit_thread(void)
|
||||
{
|
||||
if (current->thread.ubc_pc) {
|
||||
current->thread.ubc_pc = 0;
|
||||
ubc_usercnt -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
void flush_thread(void)
|
||||
{
|
||||
#if defined(CONFIG_SH_FPU)
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
flush_ptrace_hw_breakpoint(tsk);
|
||||
|
||||
#if defined(CONFIG_SH_FPU)
|
||||
/* Forget lazy FPU state */
|
||||
clear_fpu(tsk, task_pt_regs(tsk));
|
||||
clear_used_math();
|
||||
|
|
@ -195,9 +193,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
|
|||
{
|
||||
struct thread_info *ti = task_thread_info(p);
|
||||
struct pt_regs *childregs;
|
||||
#if defined(CONFIG_SH_FPU) || defined(CONFIG_SH_DSP)
|
||||
struct task_struct *tsk = current;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SH_FPU)
|
||||
unlazy_fpu(tsk, regs);
|
||||
|
|
@ -234,53 +230,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
|
|||
p->thread.sp = (unsigned long) childregs;
|
||||
p->thread.pc = (unsigned long) ret_from_fork;
|
||||
|
||||
p->thread.ubc_pc = 0;
|
||||
memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Tracing by user break controller. */
|
||||
static void ubc_set_tracing(int asid, unsigned long pc)
|
||||
{
|
||||
#if defined(CONFIG_CPU_SH4A)
|
||||
unsigned long val;
|
||||
|
||||
val = (UBC_CBR_ID_INST | UBC_CBR_RW_READ | UBC_CBR_CE);
|
||||
val |= (UBC_CBR_AIE | UBC_CBR_AIV_SET(asid));
|
||||
|
||||
ctrl_outl(val, UBC_CBR0);
|
||||
ctrl_outl(pc, UBC_CAR0);
|
||||
ctrl_outl(0x0, UBC_CAMR0);
|
||||
ctrl_outl(0x0, UBC_CBCR);
|
||||
|
||||
val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE);
|
||||
ctrl_outl(val, UBC_CRR0);
|
||||
|
||||
/* Read UBC register that we wrote last, for checking update */
|
||||
val = ctrl_inl(UBC_CRR0);
|
||||
|
||||
#else /* CONFIG_CPU_SH4A */
|
||||
ctrl_outl(pc, UBC_BARA);
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
ctrl_outb(asid, UBC_BASRA);
|
||||
#endif
|
||||
|
||||
ctrl_outl(0, UBC_BAMRA);
|
||||
|
||||
if (current_cpu_data.type == CPU_SH7729 ||
|
||||
current_cpu_data.type == CPU_SH7710 ||
|
||||
current_cpu_data.type == CPU_SH7712 ||
|
||||
current_cpu_data.type == CPU_SH7203){
|
||||
ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
|
||||
ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
|
||||
} else {
|
||||
ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA);
|
||||
ctrl_outw(BRCR_PCBA, UBC_BRCR);
|
||||
}
|
||||
#endif /* CONFIG_CPU_SH4A */
|
||||
}
|
||||
|
||||
/*
|
||||
* switch_to(x,y) should switch tasks from x to y.
|
||||
*
|
||||
|
|
@ -302,25 +256,6 @@ __switch_to(struct task_struct *prev, struct task_struct *next)
|
|||
: "r" (task_thread_info(next)));
|
||||
#endif
|
||||
|
||||
/* If no tasks are using the UBC, we're done */
|
||||
if (ubc_usercnt == 0)
|
||||
/* If no tasks are using the UBC, we're done */;
|
||||
else if (next->thread.ubc_pc && next->mm) {
|
||||
int asid = 0;
|
||||
#ifdef CONFIG_MMU
|
||||
asid |= cpu_asid(smp_processor_id(), next->mm);
|
||||
#endif
|
||||
ubc_set_tracing(asid, next->thread.ubc_pc);
|
||||
} else {
|
||||
#if defined(CONFIG_CPU_SH4A)
|
||||
ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
|
||||
ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
|
||||
#else
|
||||
ctrl_outw(0, UBC_BBRA);
|
||||
ctrl_outw(0, UBC_BBRB);
|
||||
#endif
|
||||
}
|
||||
|
||||
return prev;
|
||||
}
|
||||
|
||||
|
|
@ -412,20 +347,3 @@ unsigned long get_wchan(struct task_struct *p)
|
|||
|
||||
return pc;
|
||||
}
|
||||
|
||||
asmlinkage void break_point_trap(void)
|
||||
{
|
||||
/* Clear tracing. */
|
||||
#if defined(CONFIG_CPU_SH4A)
|
||||
ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
|
||||
ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
|
||||
#else
|
||||
ctrl_outw(0, UBC_BBRA);
|
||||
ctrl_outw(0, UBC_BBRB);
|
||||
ctrl_outl(0, UBC_BRCR);
|
||||
#endif
|
||||
current->thread.ubc_pc = 0;
|
||||
ubc_usercnt -= 1;
|
||||
|
||||
force_sig(SIGTRAP, current);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,31 +65,12 @@ static inline int put_stack_long(struct task_struct *task, int offset,
|
|||
|
||||
void user_enable_single_step(struct task_struct *child)
|
||||
{
|
||||
/* Next scheduling will set up UBC */
|
||||
if (child->thread.ubc_pc == 0)
|
||||
ubc_usercnt += 1;
|
||||
|
||||
child->thread.ubc_pc = get_stack_long(child,
|
||||
offsetof(struct pt_regs, pc));
|
||||
|
||||
set_tsk_thread_flag(child, TIF_SINGLESTEP);
|
||||
}
|
||||
|
||||
void user_disable_single_step(struct task_struct *child)
|
||||
{
|
||||
clear_tsk_thread_flag(child, TIF_SINGLESTEP);
|
||||
|
||||
/*
|
||||
* Ensure the UBC is not programmed at the next context switch.
|
||||
*
|
||||
* Normally this is not needed but there are sequences such as
|
||||
* singlestep, signal delivery, and continue that leave the
|
||||
* ubc_pc non-zero leading to spurious SIGTRAPs.
|
||||
*/
|
||||
if (child->thread.ubc_pc != 0) {
|
||||
ubc_usercnt -= 1;
|
||||
child->thread.ubc_pc = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
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