ARM: shmobile: r8a7791: add R-Car sound support on DTSI
This patch support PIO transfer only at this point Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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485f3ce67c
Коммит
09abd1fd11
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@ -985,4 +985,60 @@
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clock-names = "pcie", "pcie_bus";
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status = "disabled";
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};
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rcar_sound: rcar_sound@0xec500000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
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interrupt-parent = <&gic>;
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reg = <0 0xec500000 0 0x1000>, /* SCU */
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<0 0xec5a0000 0 0x100>, /* ADG */
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<0 0xec540000 0 0x1000>, /* SSIU */
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<0 0xec541000 0 0x1280>; /* SSI */
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clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
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<&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
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<&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
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<&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
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<&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
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<&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
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<&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
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<&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
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<&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
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<&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
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<&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
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<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
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clock-names = "ssi-all",
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"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
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"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
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"src.9", "src.8", "src.7", "src.6", "src.5",
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"src.4", "src.3", "src.2", "src.1", "src.0",
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"clk_a", "clk_b", "clk_c", "clk_i";
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status = "disabled";
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rcar_sound,src {
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src0: src@0 { };
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src1: src@1 { };
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src2: src@2 { };
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src3: src@3 { };
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src4: src@4 { };
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src5: src@5 { };
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src6: src@6 { };
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src7: src@7 { };
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src8: src@8 { };
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src9: src@9 { };
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};
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rcar_sound,ssi {
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ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
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ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
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ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
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ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
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ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
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ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
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ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
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ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
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ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
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ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
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};
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};
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};
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