PLL initialization for PLLs having both an integral and fractional mode
(rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. -----BEGIN PGP SIGNATURE----- iQEtBAABCAAXBQJYJy9BEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYEZMwf/ XPnSVfSOSXSR3A6JOc7emX5vXVcXWq3xkt98l85qhiJO8yQg+vwFk2Ur7Q22cwJI ycg6K1EAokKt7/ZE48XZ0JYXQknxxSnO7ZU0MTVQVtQB7+oWr79VY+o+WylgsSZ7 LApU2lGniYXJOnQBTfNl8Zqyrg+M+q6zTW9HwK47TH51xjUiY9K+/nyNlAuEqBWQ TR8EuOQGxIQWHzJ7HFxCO4DNGEszrRkQMOcDsp2b5rxKTF3+waQne6OhX95JZpX5 PI12A1RC8+DNvYRZlhAnrmKHDycu6QYe18ZQADs5FPihMoxK4Eh/eXzZIIgXBkXd aOc4ljF03ry8mWyKtENVCg== =2Wr8 -----END PGP SIGNATURE----- Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table
This commit is contained in:
Stephen Boyd
Коммит
09d5dc586b
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@ -319,7 +319,8 @@ static void rockchip_rk3036_pll_init(struct clk_hw *hw)
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if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
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rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
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rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
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rate->dsmpd != cur.dsmpd ||
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(!cur.dsmpd && (rate->frac != cur.frac))) {
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struct clk *parent = clk_get_parent(hw->clk);
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if (!parent) {
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@ -795,7 +796,8 @@ static void rockchip_rk3399_pll_init(struct clk_hw *hw)
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if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 ||
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rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 ||
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rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) {
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rate->dsmpd != cur.dsmpd ||
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(!cur.dsmpd && (rate->frac != cur.frac))) {
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struct clk *parent = clk_get_parent(hw->clk);
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if (!parent) {
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@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
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RK3066_PLL_RATE( 504000000, 1, 84, 4),
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RK3066_PLL_RATE( 456000000, 1, 76, 4),
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RK3066_PLL_RATE( 408000000, 1, 68, 4),
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RK3066_PLL_RATE( 400000000, 3, 100, 2),
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RK3066_PLL_RATE( 384000000, 2, 128, 4),
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RK3066_PLL_RATE( 360000000, 1, 60, 4),
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RK3066_PLL_RATE( 312000000, 1, 52, 4),
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@ -306,14 +307,14 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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RK2928_CLKGATE_CON(0), 2, GFLAGS),
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GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
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GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
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RK2928_CLKGATE_CON(0), 3, GFLAGS),
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GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
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RK2928_CLKGATE_CON(0), 6, GFLAGS),
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GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
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GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
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RK2928_CLKGATE_CON(0), 5, GFLAGS),
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GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
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GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 4, GFLAGS),
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COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
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@ -323,12 +324,12 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(1), 4, GFLAGS),
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GATE(0, "aclk_peri", "aclk_peri_pre", 0,
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GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
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RK2928_CLKGATE_CON(2), 1, GFLAGS),
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COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0,
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COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
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RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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RK2928_CLKGATE_CON(2), 2, GFLAGS),
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COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0,
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COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
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RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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RK2928_CLKGATE_CON(2), 3, GFLAGS),
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@ -77,7 +77,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
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RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
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RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
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RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
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RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
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RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
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@ -87,12 +87,13 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
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RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
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RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
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RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
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RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
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RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
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RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
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RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
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RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
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RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
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RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
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RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
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RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
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RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
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@ -410,11 +411,11 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(6), 6, GFLAGS),
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GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
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GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
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RK3399_CLKGATE_CON(13), 12, GFLAGS),
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GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
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GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
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RK3399_CLKGATE_CON(13), 12, GFLAGS),
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MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
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MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
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RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
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MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
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@ -498,7 +499,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKGATE_CON(14), 10, GFLAGS),
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GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(14), 11, GFLAGS),
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GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
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GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
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RK3399_CLKGATE_CON(0), 7, GFLAGS),
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/* big core */
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@ -539,7 +540,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(14), 2, GFLAGS),
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GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
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GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
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RK3399_CLKGATE_CON(1), 7, GFLAGS),
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/* gmac */
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@ -675,18 +676,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(18), 10, GFLAGS),
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GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
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GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
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RK3399_CLKGATE_CON(18), 12, GFLAGS),
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GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(18), 15, GFLAGS),
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GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(19), 2, GFLAGS),
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GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
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GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
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RK3399_CLKGATE_CON(4), 11, GFLAGS),
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GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
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GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
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RK3399_CLKGATE_CON(3), 5, GFLAGS),
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GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
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GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
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RK3399_CLKGATE_CON(3), 6, GFLAGS),
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/* cci */
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@ -966,7 +967,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
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GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
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GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
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GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
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GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
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GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
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GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
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GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
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@ -980,7 +981,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
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/* pclk_perilp0 gates */
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GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
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GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
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/* crypto */
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COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
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@ -72,6 +72,8 @@
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#define ACLK_IPP 200
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#define ACLK_RGA 201
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#define ACLK_CIF0 202
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#define ACLK_CPU 203
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#define ACLK_PERI 204
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/* pclk gates */
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#define PCLK_GRF 320
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@ -104,6 +106,8 @@
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#define PCLK_EFUSE 347
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#define PCLK_TZPC 348
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#define PCLK_TSADC 349
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#define PCLK_CPU 350
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#define PCLK_PERI 351
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/* hclk gates */
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#define HCLK_SDMMC 448
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@ -126,8 +130,10 @@
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#define HCLK_IPP 465
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#define HCLK_RGA 466
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#define HCLK_NANDC0 467
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#define HCLK_CPU 468
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#define HCLK_PERI 469
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#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_MCORE 2
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